公开(公告)号：US20240096790A1

公开(公告)日：2024-03-21

申请号：US17932500

申请日：2022-09-15

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5286

Abstract: Disclosed are integrated circuit structures with buried rails and backside metals for routing input signals to and/or output signals from one or more cells of the integrated circuit structures. Port landing-free connections to input ports and/or from output ports are enabled. As a result, signal routing flexibility is enhanced.

公开(公告)号：US20230115373A1

公开(公告)日：2023-04-13

申请号：US17450815

申请日：2021-10-13

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG

IPC: G06F7/50 ,  G06F1/10

Abstract: Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a method for in-memory computation. The method generally includes: accumulating, via each digital counter of a plurality of digital counters, output signals on a respective column of multiple columns of a memory, wherein a plurality of memory cells are on each of the multiple columns, the plurality of memory cells storing multiple bits representing weights of a neural network, wherein the plurality of memory cells of each of the multiple columns correspond to different word-lines of the memory; adding, via an adder circuit, output signals of the plurality of digital counters; and accumulating, via an accumulator, output signals of the adder circuit.

公开(公告)号：US20190295942A1

公开(公告)日：2019-09-26

申请号：US15933581

申请日：2018-03-23

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Kern RIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/50 ,  H01L23/532

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a signaling interconnect having a narrow trench disposed within a metallization layer, and a power rail having a wide trench disposed within the metallization layer, wherein the signaling interconnect comprises non-copper material and the power rail comprises copper. The non-copper material may include at least one of ruthenium (Ru), tungsten (W), aluminum (Al), and cobalt (Co). The signaling interconnect and power rail may be processed in a common chemical mechanical polishing step and have approximately the same trench depth. A metal cap may be deposited on top of the power rail.

公开(公告)号：US20160240437A1

公开(公告)日：2016-08-18

申请号：US15141198

申请日：2016-04-28

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri MOJUMDER ,  Mustafa BADAROGLU

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

公开(公告)号：US20160087070A1

公开(公告)日：2016-03-24

申请号：US14495562

申请日：2014-09-24

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Mustafa BADAROGLU ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L21/2254 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract translation: 体硅（Si）的一部分形成为具有翅片基底的翅片，并且在散热片基底上形成有工艺中的翅片。 翅片基底是掺杂硅，而工艺中的鳍是硅锗（SiGe）。 工艺中的SiGe鳍具有源极区和漏极区。 硼原位掺杂到漏区并进入源区。 任选地，硼通过在漏极区域和源极区域上形成具有硼的外延层进行原位掺杂，以及驱动退火以在源极区域和漏极区域中扩散硼。

公开(公告)号：US20250124284A1

公开(公告)日：2025-04-17

申请号：US18989461

申请日：2024-12-20

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG

IPC: G06N3/08 ,  G06F7/50 ,  G06F7/523 ,  G06F7/544

Abstract: Methods and apparatus for performing machine learning tasks, and in particular, to a neural-network-processing architecture and circuits for improved handling of partial accumulation results in weight-stationary operations, such as operations occurring in compute-in-memory (CIM) processing elements (PEs). One example PE circuit for machine learning generally includes an accumulator circuit, a flip-flop array having an input coupled to an output of the accumulator circuit, a write register, and a first multiplexer having a first input coupled to an output of the write register, having a second input coupled to an output of the flip-flop array, and having an output coupled to a first input of the first accumulator circuit.

公开(公告)号：US20240422995A1

公开(公告)日：2024-12-19

申请号：US18336775

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG ,  Woo Tag KANG ,  Periannan CHIDAMBARAM

IPC: H10B80/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

公开(公告)号：US20170033020A1

公开(公告)日：2017-02-02

申请号：US15293213

申请日：2016-10-13

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L21/8238 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract translation: 集成电路（IC）装置可以包括在第一类型区域中的第一类型的第一有源晶体管。 第一有源晶体管可以在第一有源晶体管的有效部分中具有第一类型功函数材料和低通道掺杂剂浓度。 IC器件还可以包括在第一类型区域中的第一类型的第一隔离晶体管。 第二有源晶体管可以具有第二类型功函数材料，并且第一隔离晶体管的有源部分中的低通道掺杂剂浓度。 第一隔离晶体管可以布置成与第一有源晶体管相邻。

公开(公告)号：US20160254261A1

公开(公告)日：2016-09-01

申请号：US14633011

申请日：2015-02-26

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L27/092 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract translation: 集成电路（IC）装置可以包括在第一类型区域中的第一类型的第一有源晶体管。 第一有源晶体管可以在第一有源晶体管的有效部分中具有第一类型功函数材料和低通道掺杂剂浓度。 IC器件还可以包括在第一类型区域中的第一类型的第一隔离晶体管。 第二有源晶体管可以具有第二类型功函数材料，并且第一隔离晶体管的有源部分中的低通道掺杂剂浓度。 第一隔离晶体管可以布置成与第一有源晶体管相邻。

公开(公告)号：US20160148936A1

公开(公告)日：2016-05-26

申请号：US14673485

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Junjing BAO ,  John Jianhong ZHU ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/285 ,  H01L21/76897 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.

Abstract translation: 半导体器件包括栅极堆叠。 该半导体器件还包括环绕接触件，布置在靠近栅极堆叠处的半导体器件的再生长源极/漏极区域的基本上所有的表面区域附近。