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公开(公告)号：US09160350B2
公开(公告)日：2015-10-13
申请号：US13676945
申请日：2012-11-14
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Masum Hossain , Pak S. Chau
IPC: H03L7/06 , H03L7/091 , G11C8/18 , H03K5/156 , H03L7/08 , H03L7/081 , H03L7/083 , H03L7/099 , H03L7/10 , G11C7/10 , G11C7/22 , G11C7/04
CPC classification number: H03L7/091 , G11C7/04 , G11C7/1057 , G11C7/222 , G11C8/18 , H03K5/1565 , H03L7/0802 , H03L7/0814 , H03L7/0816 , H03L7/083 , H03L7/0995 , H03L7/104
Abstract: Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.
Abstract translation: 描述了包括延迟锁定环（DLL）的集成电路（IC）的实施例。 一些实施例包括通过将输入时钟信号延迟第一延迟来产生第一时钟信号的第一电路，基于输入时钟信号和第一时钟信号确定代码的第二电路，以及基于输出时钟信号的第三电路 对输入时钟信号和代码。 在一些实施例中，通过在大多数时间内断电DLL电路的至少一些部分来降低DLL电路的功耗。 在一些实施例中，用于对存储器件的命令和地址电路进行时钟的时钟信号用于对片上终端等待时间计数器电路进行时钟。
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12.发明申请公开(公告)号：US20140380082A1
公开(公告)日：2014-12-25
申请号：US14482782
申请日：2014-09-10
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
Abstract translation: 描述能够通过使用注入锁定振荡器执行分数时钟倍增的电路。 本文描述的一些实施例通过周期性地改变喷射位置，从喷射信号的一组注入位置周期性地改变喷射位置，和/或通过周期性地改变注入的注入信号的相位相位来改变相位 进入国际劳工组织。
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公开(公告)号：US20130271186A1
公开(公告)日：2013-10-17
申请号：US13830007
申请日：2013-03-14
Applicant: RAMBUS INC.
Inventor： Masum Hossain , Farshid Aryanfar
IPC: H03L7/23
CPC classification number: H03L7/235 , H03L7/0805 , H03L7/081 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L7/23
Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
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公开(公告)号：US11811379B2
公开(公告)日：2023-11-07
申请号：US17559960
申请日：2021-12-22
Applicant: Rambus Inc.
Inventor： Masum Hossain , Carl W. Werner
CPC classification number: H03H11/1239 , H04B1/0458 , H04B1/109 , H04B1/588 , H04B2001/045
Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.
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15.发明授权公开(公告)号：US11770275B2
公开(公告)日：2023-09-26
申请号：US17852278
申请日：2022-06-28
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Charles Walter Boecker
IPC: H04L25/03
CPC classification number: H04L25/03057
Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.
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Patent Agency Ranking
公开(公告)号：US11211960B2
公开(公告)日：2021-12-28
申请号：US17114782
申请日：2020-12-08
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd , Wendemagegnehu Beyene
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US10951218B2
公开(公告)日：2021-03-16
申请号：US16813156
申请日：2020-03-09
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
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公开(公告)号：US10892791B2
公开(公告)日：2021-01-12
申请号：US16680859
申请日：2019-11-12
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd , Wendemagegnehu Beyene
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US10516427B2
公开(公告)日：2019-12-24
申请号：US15755255
申请日：2016-10-12
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd , Wendemagegnehu Beyene
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US10050771B2
公开(公告)日：2018-08-14
申请号：US15677467
申请日：2017-08-15
Applicant: Rambus Inc.
Inventor： Masum Hossain , Brian Leibowitz , Jihong Ren
CPC classification number: H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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