-
公开(公告)号：US12074623B2
公开(公告)日：2024-08-27
申请号：US18144342
申请日：2023-05-08
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd , Wendemagegnehu Beyene
CPC classification number: H04B1/123 , H04B1/12 , H04L25/0264 , H04L25/03057 , H04L25/03076 , H04L25/03133 , H04L25/4917 , H04L27/00 , H04L27/01 , H04L27/06
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
-
2.发明公开公开(公告)号：US20240168873A1
公开(公告)日：2024-05-23
申请号：US18162824
申请日：2021-08-06
Applicant: Rambus Inc.
Inventor： Andrew M. Fuller , Barry William Daly , Thomas J. Giovannini , Lei Luo , Masum Hossain
IPC: G06F12/02 , G11C11/408
CPC classification number: G06F12/0223 , G11C11/4082
Abstract: Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer in a set has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a timing-reference signal (e.g. a clock or strobe) that is common to the set. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.
-
公开(公告)号：US11876652B2
公开(公告)日：2024-01-16
申请号：US17400823
申请日：2021-08-12
Applicant: Rambus Inc.
Inventor： Masum Hossain , Maruf H. Mohammad
CPC classification number: H04L25/4917 , H04L25/03019 , H04L25/03178
Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.
-
公开(公告)号：US20190222217A1
公开(公告)日：2019-07-18
申请号：US16247894
申请日：2019-01-15
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
CPC classification number: H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
-
公开(公告)号：US20190052490A1
公开(公告)日：2019-02-14
申请号：US16113900
申请日：2018-08-27
Applicant: Rambus Inc.
Inventor： Masum Hossain , Maruf H. Mohammad
Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.
-
Patent Agency Ranking
公开(公告)号：US20180167076A1
公开(公告)日：2018-06-14
申请号：US15818434
申请日：2017-11-20
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
-
公开(公告)号：US20170033918A1
公开(公告)日：2017-02-02
申请号：US15212514
申请日：2016-07-18
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Yikui Jen Dong , Arash Zargaran-Yazd
CPC classification number: H04L7/0087 , H03K7/02 , H03L7/00 , H04L7/0025 , H04L7/0337 , H04L25/4917
Abstract: A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.
Abstract translation: 接收器串行数据流通过将本地时钟相位对准数据流中的转换，从近似频率参考时钟产生本地定时参考时钟。 这个过程通常被称为时钟和数据恢复（CDR）。 选择数据信号的某些转换用于对准本地时钟，并忽略某些转换。 来自接收多个串行数据流的多个接收机的相位误差信号被组合并用于对频率参考时钟进行共同的相位调整。 这些通用调整跟踪所接收数据流通用的抖动。 使用本地相位误差信号来进行使各个本地时钟更好地对准其相应串行数据流的转换的本地调整。 这些本地调整跟踪每个相应串行数据流更独特的抖动。
-
公开(公告)号：US20160233871A1
公开(公告)日：2016-08-11
申请号：US15130802
申请日：2016-04-15
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
CPC classification number: H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
Abstract translation: 在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。 在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。 在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。 响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择 时钟。
-
公开(公告)号：US20160190986A1
公开(公告)日：2016-06-30
申请号：US14960065
申请日：2015-12-04
Applicant: Rambus Inc.
Inventor： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
CPC classification number: H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
-
公开(公告)号：US09209966B1
公开(公告)日：2015-12-08
申请号：US14687766
申请日：2015-04-15
Applicant: Rambus Inc.
Inventor： Masum Hossain , Jared L. Zerbe , Myeong-Jae Park
CPC classification number: H04L7/0331 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/03146 , H04L2025/03445
Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.
-
-
-
-
-
-
-
-
-
Search Results
80
records
(took 0.036 seconds)
