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    INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP
    1.
    发明申请
    INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP 审中-公开
    包含延迟环路的集成电路

    公开(公告)号：US20130121094A1

    公开(公告)日：2013-05-16

    申请号：US13676945

    申请日：2012-11-14

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Masum Hossain ,  Pak S. Chau

    IPC: H03L7/091 ,  G11C8/18

    CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/222 ,  G11C8/18 ,  H03K5/1565 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/083 ,  H03L7/0995 ,  H03L7/104

    Abstract: Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.

    Abstract translation: 描述了包括延迟锁定环（DLL）的集成电路（IC）的实施例。 一些实施例包括通过将输入时钟信号延迟第一延迟来产生第一时钟信号的第一电路，基于输入时钟信号和第一时钟信号确定代码的第二电路，以及基于输出时钟信号的第三电路 对输入时钟信号和代码。 在一些实施例中，通过在大多数时间内断电DLL电路的至少一些部分来降低DLL电路的功耗。 在一些实施例中，用于对存储器件的命令和地址电路进行时钟的时钟信号用于对片上终端等待时间计数器电路进行时钟。

    Integrated circuit comprising a delay-locked loop
    6.
    发明授权
    Integrated circuit comprising a delay-locked loop 有权
    集成电路包括延迟锁定环路

    公开(公告)号：US09160350B2

    公开(公告)日：2015-10-13

    申请号：US13676945

    申请日：2012-11-14

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Masum Hossain ,  Pak S. Chau

    IPC: H03L7/06 ,  H03L7/091 ,  G11C8/18 ,  H03K5/156 ,  H03L7/08 ,  H03L7/081 ,  H03L7/083 ,  H03L7/099 ,  H03L7/10 ,  G11C7/10 ,  G11C7/22 ,  G11C7/04

    CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/222 ,  G11C8/18 ,  H03K5/1565 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/083 ,  H03L7/0995 ,  H03L7/104

    Abstract: Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry.

    Abstract translation: 描述了包括延迟锁定环（DLL）的集成电路（IC）的实施例。 一些实施例包括通过将输入时钟信号延迟第一延迟来产生第一时钟信号的第一电路，基于输入时钟信号和第一时钟信号确定代码的第二电路，以及基于输出时钟信号的第三电路 对输入时钟信号和代码。 在一些实施例中，通过在大多数时间内断电DLL电路的至少一些部分来降低DLL电路的功耗。 在一些实施例中，用于对存储器件的命令和地址电路进行时钟的时钟信号用于对片上终端等待时间计数器电路进行时钟。

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