公开(公告)号：US20150270394A1

公开(公告)日：2015-09-24

申请号：US14733557

申请日：2015-06-08

Applicant: Renesas Electronics Corporation

Inventor： Toshiyuki TAKEWAKI ,  Hironobu MIYAMOTO

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/49 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/7843 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/475 ,  H01L29/4966 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/80

Abstract: A semiconductor device includes a substrate, a buffer layer provided on the substrate, a channel layer provided on the buffer layer, an electron supply layer provided on the channel layer, a first contact hole provided on the electron supply layer, a source electrode that is formed within the first contact hole, and electrically connected to the electron supply layer, a second contact hole provided on the electron supply layer, a drain electrode that is formed within the second contact hole, and electrically connected to the electron supply layer, a gate electrode provided between the source electrode and the drain electrode, a second insulating film that is formed to cover the gate electrode, a strain relaxation film that is formed over the second insulating film above the gate electrode, a third insulating film that is formed to cover the source electrode, the drain electrode, and the strain relaxation film, and an organic film that is formed over the third insulating film.

Abstract translation: 半导体器件包括衬底，设置在衬底上的缓冲层，设置在缓冲层上的沟道层，设置在沟道层上的电子供给层，设置在电子供给层上的第一接触孔， 形成在第一接触孔内，电连接到电子供给层，设置在电子供给层上的第二接触孔，形成在第二接触孔内并与电子供给层电连接的漏电极， 设置在源电极和漏电极之间的电极，形成为覆盖栅电极的第二绝缘膜，形成在栅电极上方的第二绝缘膜上的应变松弛膜，形成为覆盖的第三绝缘膜 源电极，漏电极和应变松弛膜，以及形成在第三绝缘膜上的有机膜。

公开(公告)号：US20240290881A1

公开(公告)日：2024-08-29

申请号：US18638883

申请日：2024-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66068 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0274 ,  H01L29/0696 ,  H01L29/45 ,  H01L29/4916

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20210028082A1

公开(公告)日：2021-01-28

申请号：US15931230

申请日：2020-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI ,  Hironobu MIYAMOTO ,  Masami SAWADA

IPC: H01L23/367 ,  H01L23/373 ,  H01L29/24 ,  H01L29/20 ,  H01L29/16

Abstract: A Semiconductor device includes a substrate and a thermal conductive film. The substrate has a top surface and a back surface which oppose with each other. A first opening is formed on the back surface of substrate. The thermal conductive film includes a first thermal conductive portion formed in the first opening. The first thermal conductive portion is embedded in the first opening such that a void is formed in the first opening.

公开(公告)号：US20190288105A1

公开(公告)日：2019-09-19

申请号：US16282981

申请日：2019-02-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI ,  Hironobu MIYAMOTO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266 ,  H01L21/308

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

公开(公告)号：US20180308968A1

公开(公告)日：2018-10-25

申请号：US15904701

申请日：2018-02-26

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/417 ,  H01L29/47 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/0273 ,  H01L21/28581 ,  H01L21/30621 ,  H01L21/32139 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/475 ,  H01L29/66462

Abstract: Characteristics of a semiconductor device are improved.A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.

公开(公告)号：US20170288046A1

公开(公告)日：2017-10-05

申请号：US15463320

申请日：2017-03-20

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Hiroshi KAWAGUCHI ,  Tatsuo NAKAYAMA

IPC: H01L29/778 ,  H01L29/417 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L29/7787 ,  H01L21/0254 ,  H01L21/30612 ,  H01L29/0657 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/7786

Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (θ1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.

公开(公告)号：US20160005846A1

公开(公告)日：2016-01-07

申请号：US14829216

申请日：2015-08-18

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alxα1-xN layer (α includes Ga or In, and 0

Abstract translation: 半导体器件包括第一半导体层，形成在第一半导体层上的第二半导体层，与第二半导体层接触的栅极绝缘膜，以及经由栅极绝缘膜与第二半导体层相对的栅电极。 第一半导体层包括Al xα1-x N层（α包括Ga或In，并且0

公开(公告)号：US20140264274A1

公开(公告)日：2014-09-18

申请号：US14198430

申请日：2014-03-05

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Ryohei NEGA ,  Masaaki KANAZAWA ,  Takashi INOUE

IPC: H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/7787

Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.

Abstract translation: 提高半导体器件的性能。 例如，假设超晶格层被插入在缓冲层和沟道层之间，则导入形成超晶格层的一部分的氮化物半导体层中的受主的浓度高于形成氮化物半导体层的受主的浓度 超晶格层的另一部分。 也就是说，导入具有小带隙的氮化物半导体层的受主的浓度高于导入具有大带隙的氮化物半导体层的受主的浓度。

公开(公告)号：US20140209980A1

公开(公告)日：2014-07-31

申请号：US14229645

申请日：2014-03-28

Applicant: Renesas Electronics Corporation

Inventor： Takashi INOUE ,  Tatsuo NAKAYAMA ,  Yasuhiro OKAMOTO ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride semiconductor over the buffer layer, forming a barrier layer made of a nitride semiconductor over the channel layer, forming a cap layer made of a nitride semiconductor over the barrier layer, forming a gate insulating film so as to in contact with the cap layer; and forming a gate electrode over the gate insulating film, wherein compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer by controlling compositions of the cap layer, the barrier layer, the channel layer, and the buffer layer.

Abstract translation: 一种半导体器件的制造方法，包括：形成由氮化物半导体构成的缓冲层，在所述缓冲层上形成由氮化物半导体构成的沟道层，在所述沟道层上形成由氮化物半导体构成的阻挡层，形成覆盖层 由阻挡层上的氮化物半导体形成，形成栅极绝缘膜以与盖层接触; 以及在所述栅极绝缘膜上形成栅电极，其中在所述覆盖层和所述阻挡层之间的界面处产生压缩应变，以及在所述沟道层和所述缓冲层之间的界面处产生压应变，并且在所述栅极之间的界面处产生拉伸应变 层和沟道层，通过控制盖层，阻挡层，沟道层和缓冲层的组成。

公开(公告)号：US20230207689A1

公开(公告)日：2023-06-29

申请号：US18174952

申请日：2023-02-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI ,  Hironobu MIYAMOTO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/1608 ,  H01L29/66545 ,  H01L29/66734 ,  H01L21/3086 ,  H01L29/0865 ,  H01L21/046 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/266 ,  H01L29/66068

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.