公开(公告)号：US20240186255A1

公开(公告)日：2024-06-06

申请号：US18074265

申请日：2022-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi OIKAWA

IPC: H01L23/538 ,  H01L25/065 ,  H04L7/00 ,  H04L25/03 ,  H10B12/00

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L27/108 ,  H04L7/0079 ,  H04L25/03878

Abstract: An electronic device includes: a first semiconductor device having a plurality of transmitting units; a second semiconductor device having a plurality of receiving units; and a plurality of wirings coupling between the plurality of transmitting units and the plurality of receiving units and also transmitting a data signal from the plurality of transmitting units to the plurality of receiving units. Here, the plurality of wirings has: a plurality of first wirings each having a signal delay that is divisible by a half of a time of the data signal; and a plurality of second wirings each having a signal delay that is not divisible by the half of the time of the data signal. The plurality of first wirings is arranged at a first wiring interval. Also, the plurality of second wirings is arranged at a second wiring interval wider than the first wiring interval.

公开(公告)号：US20190377143A1

公开(公告)日：2019-12-12

申请号：US16410733

申请日：2019-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuaki TSUCHIYAMA ,  Motoo SUWA ,  Ryuichi OIKAWA

IPC: G02B6/42 ,  H01S5/042

Abstract: A performance of an electronic device is improved. An optical transceiver (electronic device) includes a semiconductor device electrically connected to a transmission line. In this semiconductor device, a resistor is arranged between a wiring electrically connected to the transmission line and a semiconductor chip having a semiconductor laser formed therein.

公开(公告)号：US20190229088A1

公开(公告)日：2019-07-25

申请号：US16223766

申请日：2018-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi OIKAWA

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18

Abstract: Cross talk among wirings formed in an interposer is reduced while increase in a parasitic capacitance among the wirings formed in the interposer is suppressed. A semiconductor device has an interposer including a first wiring layer, a second wiring layer formed above the first wiring layer, and a third wiring layer formed above the second wiring layer. In a plan view, a first signal wiring formed in the first wiring layer and a reference wiring formed in the second wiring layer are distant from each other. Similarly, in a plan view, the reference wiring formed in the second wiring layer and a third signal wiring formed in a third wiring layer are distant from each other.

公开(公告)号：US20180374787A1

公开(公告)日：2018-12-27

申请号：US15976388

申请日：2018-05-10

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA

IPC: H01L23/498 ,  H01L23/66

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: To improve signal transmission characteristics of a high frequency signal of 80 GHz or higher. A semiconductor device includes a wiring board having a structure in which a signal via structure and a grounding via structure have mutually overlapping portions in plan view.

公开(公告)号：US20170263693A1

公开(公告)日：2017-09-14

申请号：US15378535

申请日：2016-12-14

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA

IPC: H01L49/02 ,  H01L25/065 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/49833 ,  H01L23/5223 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: A semiconductor device includes a capacitive element that has frequency dependency that a capacitance value obtained when a second frequency signal that is higher in frequency than a first frequency signal has been applied becomes smaller than a capacitance value obtained when the first frequency signal has been applied and thereby improvement of performance of the semiconductor device is promoted.

公开(公告)号：US20250029933A1

公开(公告)日：2025-01-23

申请号：US18770072

申请日：2024-07-11

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Shuuichi KARIYAZAKI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

Abstract: The performance of an electronic device can be improved. The electronic device includes a wiring substrate, a semiconductor memory device disposed on the wiring substrate, and a semiconductor control device disposed on the wiring substrate. The wiring substrate includes a first fixed potential wiring and a second fixed potential wiring, and a plurality of signal wirings arranged between the first fixed potential wiring and the second fixed potential wiring. The plurality of signal wirings includes a first signal wiring adjacent to the first fixed potential wiring, a second signal wiring adjacent to the first signal wiring, and a third signal wiring adjacent to the second signal wiring. A first distance between the first signal wiring and the second signal wiring is smaller than a second distance between the second signal wiring and the third signal wiring.

公开(公告)号：US20230335512A1

公开(公告)日：2023-10-19

申请号：US17720689

申请日：2022-04-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi KARIYAZAKI ,  Ryuichi OIKAWA

IPC: H01L23/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01P3/08

CPC classification number: H01L23/66 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/16 ,  H01L23/49822 ,  H01L23/49838 ,  H01P3/08 ,  H01L2223/6627 ,  H01L2224/16157 ,  H01L2924/19031 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: The wiring board has a first region overlapping a first semiconductor device and a second region not overlapping each of the first semiconductor device and a second semiconductor device. A first signal wiring of the wiring board has a first portion in the first region and a second portion in the second region. In a thickness direction of the wiring board, the second portion is between two ground patterns to which a reference potential is supplied, while the first portion has a portion not positioned between two ground patterns to which a reference potential is supplied. The first portion has a first wide portion having a larger width than a width of the second portion.

公开(公告)号：US20200235068A1

公开(公告)日：2020-07-23

申请号：US16732020

申请日：2019-12-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi OIKAWA

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/552

Abstract: The semiconductor device includes a solder ball connected to a pad, and located below the pad, a first wiring electrically connected to the pad, and located above the pad, and a second wiring electrically connected to the first wiring. At this time, a width of the first wiring is greater than a width of the second wiring. Accordingly, high-frequency noise can be reduced while improving signal transmission characteristics.

公开(公告)号：US20170213776A1

公开(公告)日：2017-07-27

申请号：US15515465

申请日：2014-12-24

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Toshihiko OCHIAI ,  Shuuichi KARIYAZAKI ,  Yuji KAYASHIMA ,  Tsuyoshi KIDA

IPC: H01L23/14 ,  H01L25/065 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L23/147 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

公开(公告)号：US20160190049A1

公开(公告)日：2016-06-30

申请号：US15059948

申请日：2016-03-03

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Ryuichi OIKAWA

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5225 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K1/0225 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09681 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.