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公开(公告)号:US20180012645A1
公开(公告)日:2018-01-11
申请号:US15710639
申请日:2017-09-20
Applicant: Renesas Electronics Corporation
Inventor: Toru HAYASHI , Motoo SUWA
IPC: G11C11/4076 , G06F1/12 , G11C7/10 , G11C11/4096 , G11C5/06
CPC classification number: G11C11/4076 , G06F1/12 , G11C5/063 , G11C7/10 , G11C11/4096 , H01L2224/16227 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
Abstract: An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.
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公开(公告)号:US20170033070A1
公开(公告)日:2017-02-02
申请号:US15168550
申请日:2016-05-31
Applicant: Renesas Electronics Corporation
Inventor: Takafumi BETSUI , Motoo SUWA
IPC: H01L23/00 , H01L25/065 , H01L23/498
CPC classification number: H01L24/17 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L25/0655 , H01L2224/16227 , H01L2924/1016 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105
Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.
Abstract translation: 可以防止尺寸增大的半导体装置。 半导体器件包括具有第一主表面和与第一主表面相对的第二主表面的半导体芯片和布线基板,半导体芯片的第二主表面安装在该基板上,使得半导体芯片的第二主表面面向第一主表面 布线基板。 在半导体芯片的第二主表面上,布置有与第一电路连接的多个第一端子和与第二电路连接的多个第二端子。 多个第一端子的布置图案和多个第二端子的布置图案包括相同的布置图案。 在从半导体芯片的第一主表面观察第一电路接近第二电路的布线基板的区域中形成向第一电路提供电源电压的电压线。 在第二电路接近第一电路的布线基板的区域中,形成向第二电路供给电源电压的电压线。
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公开(公告)号:US20200083663A1
公开(公告)日:2020-03-12
申请号:US16544363
申请日:2019-08-19
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Kazuaki TSUCHIYAMA , Motoo SUWA , Hidemasa TAKAHASHI
Abstract: Improve semiconductor device performance. The wiring WL1A on which the semiconductor chip CHP1 in which the semiconductor lasers LD is formed is mounted has a stub STB2 in the vicinity of the mounting area of the semiconductor chip CHP1.
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公开(公告)号:US20170032832A1
公开(公告)日:2017-02-02
申请号:US15178091
申请日:2016-06-09
Applicant: Renesas Electronics Corporation
Inventor: Motoo SUWA , Takafumi BETSUI
IPC: G11C11/4076 , H01L23/498 , H01L27/108
CPC classification number: G11C11/4076 , G11C5/063 , H01L23/498 , H01L23/49816 , H01L23/49827 , H01L23/49844 , H01L23/5381 , H01L23/5383 , H01L23/5386 , H01L27/108 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192 , H01L2924/15311
Abstract: To provide an electronic device capable of improving a signal quality.The electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.
Abstract translation: 电子设备包括半导体存储器件,半导体器件,被配置为访问存储在半导体存储器件中的数据;以及布线基板,其上安装有半导体存储器件和半导体器件。 布线基板包括通过第一和第二布线层将半导体器件与半导体存储器件的每个第一和第二数据端电连接的第一和第二数据布线。 第一布线层是比第二布线层更靠近半导体器件配置的布线层,并且第一数据端子比第二数据端子位于比半导体器件更远的位置。
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公开(公告)号:US20150234758A1
公开(公告)日:2015-08-20
申请号:US14696372
申请日:2015-04-24
Applicant: Renesas Electronics Corporation
Inventor: Yasuhiro YOSHIKAWA , Motoo SUWA
CPC classification number: G06F13/287 , G06F13/385 , G06F13/4068 , G11C7/1072 , H01L23/49816 , H01L23/49838 , H01L23/552 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/05554 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/10162 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H05K1/0216 , H01L2224/32225 , H01L2924/00012 , H01L2224/13099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: There is a need to alleviate or reduce crosstalk between bonding wires or wires in a device substrate. One selection configuration divides a multiplexed terminal group into three groups according to functions differently from another selection configuration that divides the multiplexed terminal group into two groups. A first multi-pin semiconductor device is configured such that the groups are successively arranged along one edge of the chip. The first semiconductor device connects with a second semiconductor device via a multiplexed terminal group. The multiplexed terminal group includes first through third interface terminal groups that differ from each other in signal input/output configurations.
Abstract translation: 需要减轻或减少器件衬底中的接合线或导线之间的串扰。 一种选择配置根据功能将多路复用终端组划分为三组,与将多路复用终端组划分为两组的另一选择配置不同。 第一多针半导体器件被配置为使得这些组沿着芯片的一个边缘依次布置。 第一半导体器件经由多路复用端子组与第二半导体器件连接。 多路复用终端组包括在信号输入/输出配置中彼此不同的第一至第三接口端子组。
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公开(公告)号:US20180068971A1
公开(公告)日:2018-03-08
申请号:US15795365
申请日:2017-10-27
Applicant: Renesas Electronics Corporation
Inventor: Takafumi BETSUI , Motoo SUWA
IPC: H01L23/00 , H01L23/498 , H01L25/065
CPC classification number: H01L24/17 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L25/0655 , H01L2224/16227 , H01L2924/1016 , H01L2924/1431 , H01L2924/1432 , H01L2924/1436 , H01L2924/1438 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105
Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.
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公开(公告)号:US20170243630A1
公开(公告)日:2017-08-24
申请号:US15589166
申请日:2017-05-08
Applicant: Renesas Electronics Corporation
Inventor: Toru HAYASHI , Motoo SUWA
IPC: G11C11/4076 , G11C11/4096 , G06F1/12
CPC classification number: G11C11/4076 , G06F1/12 , G11C5/063 , G11C7/10 , G11C11/4096 , H01L2224/16227 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
Abstract: An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.
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公开(公告)号:US20170062021A1
公开(公告)日:2017-03-02
申请号:US15351600
申请日:2016-11-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Takafumi BETSUI , Naoto TAOKA , Motoo SUWA , Shigezumi MATSUI , Norihiko SUGITA , Yoshiharu FUKUSHIMA
IPC: G11C5/04
CPC classification number: G11C5/04 , G11C5/02 , G11C5/06 , G11C5/063 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/17 , H01L25/18 , H01L2224/16 , H01L2224/16227 , H01L2224/49175 , H01L2924/1432 , H01L2924/14361 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H05K1/0237 , H05K1/181 , H05K3/4602 , H05K2201/09236 , H05K2201/093 , H05K2201/09663 , H05K2201/10159 , H05K2201/10522 , H05K2201/10734 , Y02P70/611 , H01L2924/00
Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
Abstract translation: 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下,与仅在一侧具有存储器接口电路的半导体板相比,可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此,微型计算机在主板和模块板上简化了线路设计。
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公开(公告)号:US20170032834A1
公开(公告)日:2017-02-02
申请号:US15170535
申请日:2016-06-01
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Motoo SUWA , Takafumi BETSUI , Masato SUZUKI
IPC: G11C11/408 , H01L25/065 , G11C5/06 , H01L23/528 , G11C5/02 , H01L23/498 , H01L23/522
CPC classification number: G11C5/063 , G11C5/025 , G11C11/4082 , G11C11/4093 , G11C2207/105 , H01L23/5228 , H01L23/5283 , H01L23/5386 , H01L23/647 , H01L25/0655 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
Abstract: The number of terminals included in a semiconductor device which is included in an electronic device is reduced. The electronic device includes: a first semiconductor device having first and second input terminals; a second semiconductor device having a first output terminal and a first driver circuit to drive the first output terminal; and a wiring substrate over which the first and second semiconductor devices are mounted. The first and second input terminals are commonly coupled to the first output terminal via a first line formed on the wiring substrate. A composite resistance value of first and second termination resistors coupled to the first and second input terminals, respectively, is equivalent to a drive impedance of the first driver circuit.
Abstract translation: 包括在包括在电子设备中的半导体器件中的终端的数量减少。 电子设备包括:具有第一和第二输入端的第一半导体器件; 具有第一输出端和驱动所述第一输出端的第一驱动电路的第二半导体器件; 以及安装有第一和第二半导体器件的布线基板。 第一和第二输入端通常经由形成在布线基板上的第一线耦合到第一输出端。 分别耦合到第一和第二输入端的第一和第二终端电阻的复合电阻值等于第一驱动电路的驱动阻抗。
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公开(公告)号:US20190377143A1
公开(公告)日:2019-12-12
申请号:US16410733
申请日:2019-05-13
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Kazuaki TSUCHIYAMA , Motoo SUWA , Ryuichi OIKAWA
Abstract: A performance of an electronic device is improved. An optical transceiver (electronic device) includes a semiconductor device electrically connected to a transmission line. In this semiconductor device, a resistor is arranged between a wiring electrically connected to the transmission line and a semiconductor chip having a semiconductor laser formed therein.
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