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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20170033070A1

    公开(公告)日：2017-02-02

    申请号：US15168550

    申请日：2016-05-31

    Applicant: Renesas Electronics Corporation

    Inventor： Takafumi BETSUI ,  Motoo SUWA

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

    CPC classification number: H01L24/17 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105

    Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.

    Abstract translation: 可以防止尺寸增大的半导体装置。 半导体器件包括具有第一主表面和与第一主表面相对的第二主表面的半导体芯片和布线基板，半导体芯片的第二主表面安装在该基板上，使得半导体芯片的第二主表面面向第一主表面 布线基板。 在半导体芯片的第二主表面上，布置有与第一电路连接的多个第一端子和与第二电路连接的多个第二端子。 多个第一端子的布置图案和多个第二端子的布置图案包括相同的布置图案。 在从半导体芯片的第一主表面观察第一电路接近第二电路的布线基板的区域中形成向第一电路提供电源电压的电压线。 在第二电路接近第一电路的布线基板的区域中，形成向第二电路供给电源电压的电压线。

    ELECTRONIC DEVICE
    4.
    发明申请
    ELECTRONIC DEVICE 有权
    电子设备

    公开(公告)号：US20170032832A1

    公开(公告)日：2017-02-02

    申请号：US15178091

    申请日：2016-06-09

    Applicant: Renesas Electronics Corporation

    Inventor： Motoo SUWA ,  Takafumi BETSUI

    IPC: G11C11/4076 ,  H01L23/498 ,  H01L27/108

    CPC classification number: G11C11/4076 ,  G11C5/063 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L27/108 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311

    Abstract: To provide an electronic device capable of improving a signal quality.The electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.

    Abstract translation: 电子设备包括半导体存储器件，半导体器件，被配置为访问存储在半导体存储器件中的数据;以及布线基板，其上安装有半导体存储器件和半导体器件。 布线基板包括通过第一和第二布线层将半导体器件与半导体存储器件的每个第一和第二数据端电连接的第一和第二数据布线。 第一布线层是比第二布线层更靠近半导体器件配置的布线层，并且第一数据端子比第二数据端子位于比半导体器件更远的位置。

    SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180068971A1

    公开(公告)日：2018-03-08

    申请号：US15795365

    申请日：2017-10-27

    Applicant: Renesas Electronics Corporation

    Inventor： Takafumi BETSUI ,  Motoo SUWA

    IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

    CPC classification number: H01L24/17 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105

    Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.

    ELECTRONIC DEVICE
    7.
    发明申请
    ELECTRONIC DEVICE 有权

    公开(公告)号：US20170243630A1

    公开(公告)日：2017-08-24

    申请号：US15589166

    申请日：2017-05-08

    Applicant: Renesas Electronics Corporation

    Inventor： Toru HAYASHI ,  Motoo SUWA

    IPC: G11C11/4076 ,  G11C11/4096 ,  G06F1/12

    CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C5/063 ,  G11C7/10 ,  G11C11/4096 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/00014

    Abstract: An electronic device includes a substrate including an upper surface, a clock output pad formed in a control device mounting area of the upper surface, a command/address output pad formed in the control device mounting area, a clock signal main wiring connected to the clock output pad, a command/address signal main wiring connected to the command/address output pad, a first clock signal branch wiring branched from the clock signal main wiring at a first branch point of the clock signal main wiring, and a second clock signal branch wiring branched from the clock signal main wiring at a second branch point of the clock signal main wiring, which is located at a downstream side of the clock signal main wiring than the first branch point of the clock signal main wiring.

    ELECTRONIC DEVICE
    9.
    发明申请
    ELECTRONIC DEVICE 有权
    电子设备

    公开(公告)号：US20170032834A1

    公开(公告)日：2017-02-02

    申请号：US15170535

    申请日：2016-06-01

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Motoo SUWA ,  Takafumi BETSUI ,  Masato SUZUKI

    IPC: G11C11/408 ,  H01L25/065 ,  G11C5/06 ,  H01L23/528 ,  G11C5/02 ,  H01L23/498 ,  H01L23/522

    CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C11/4082 ,  G11C11/4093 ,  G11C2207/105 ,  H01L23/5228 ,  H01L23/5283 ,  H01L23/5386 ,  H01L23/647 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311

    Abstract: The number of terminals included in a semiconductor device which is included in an electronic device is reduced. The electronic device includes: a first semiconductor device having first and second input terminals; a second semiconductor device having a first output terminal and a first driver circuit to drive the first output terminal; and a wiring substrate over which the first and second semiconductor devices are mounted. The first and second input terminals are commonly coupled to the first output terminal via a first line formed on the wiring substrate. A composite resistance value of first and second termination resistors coupled to the first and second input terminals, respectively, is equivalent to a drive impedance of the first driver circuit.

    Abstract translation: 包括在包括在电子设备中的半导体器件中的终端的数量减少。 电子设备包括：具有第一和第二输入端的第一半导体器件; 具有第一输出端和驱动所述第一输出端的第一驱动电路的第二半导体器件; 以及安装有第一和第二半导体器件的布线基板。 第一和第二输入端通常经由形成在布线基板上的第一线耦合到第一输出端。 分别耦合到第一和第二输入端的第一和第二终端电阻的复合电阻值等于第一驱动电路的驱动阻抗。

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