公开(公告)号：US20150214142A1

公开(公告)日：2015-07-30

申请号：US14590291

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Ryuichi OIKAWA

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5225 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K1/0225 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09681 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.

Abstract translation: 为了提高半导体器件的抗噪声性。 半导体器件的布线基板包括形成有信号发送线的第一布线层和与第一布线层的上层或下层相邻地安装的第二布线层。 第二布线层包括在厚度方向上与导线23的一部分重叠的位置处形成开口部的导体平面和安装在导体平面的开口部内的导体图案。 导体图案包括与导体平面隔离的主图案部分（网格图案部分）和耦合主图案部分和导体平面的多个耦合部分。

公开(公告)号：US20220165672A1

公开(公告)日：2022-05-26

申请号：US17517955

申请日：2021-11-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi OIKAWA

IPC: H01L23/538 ,  H01L25/065 ,  H04B10/50 ,  H04B10/40

Abstract: A first semiconductor element (laser diode) and a second semiconductor element (laser diode) are connected to each other in series between a wiring electrically connected to an anode of the first semiconductor element and a wiring electrically connected to a cathode of the second semiconductor element. In this case, each of the first semiconductor element and the second semiconductor element includes a laminated pattern having an emission layer and a plurality of semiconductor layers covering this laminated pattern.

公开(公告)号：US20210159166A1

公开(公告)日：2021-05-27

申请号：US17068422

申请日：2020-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi OIKAWA

IPC: H01L23/522 ,  H01L23/64 ,  H05K1/02 ,  H01L49/02 ,  H01L23/528

Abstract: A semiconductor device comprises a wiring substrate and a semiconductor chip. In the wiring substrate, a plurality of micro-elements each comprised of a stacked structure including a power supply pattern and a ground pattern is arranged at a predetermined interval. In each of the plurality of micro-elements, the power supply pattern is formed in a wiring layer located one layer above or one layer below a wiring layer in which the ground pattern is formed. A power supply potential is to be supplied to the power supply patter, and a ground potential is to be supplied to the ground patter.

公开(公告)号：US20180151460A1

公开(公告)日：2018-05-31

申请号：US15879610

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Toshihiko OCHIAI ,  Shuuichi KARIYAZAKI ,  Yuji KAYASHIMA ,  Tsuyoshi KIDA

IPC: H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L23/66

CPC classification number: H01L23/147 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

公开(公告)号：US20170141812A1

公开(公告)日：2017-05-18

申请号：US15298563

申请日：2016-10-20

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA

IPC: H04B3/18 ,  H03K5/159 ,  H01L25/10 ,  H03K19/20 ,  H01L23/498 ,  H01L23/31

CPC classification number: H04B3/18 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/1058 ,  H01L2924/15311 ,  H03K5/159 ,  H03K19/20 ,  H04B2203/00 ,  H04L25/0264 ,  H04L25/0288 ,  H04L25/085

Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes waveform of a signal at the end of the signal line.

公开(公告)号：US20230335513A1

公开(公告)日：2023-10-19

申请号：US17720699

申请日：2022-04-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi OIKAWA

IPC: H01L23/66 ,  G06F30/3953 ,  H03K5/01

CPC classification number: H01L23/66 ,  G06F30/3953 ,  H03K5/01 ,  H01L2223/6638

Abstract: The designing method according to an embodiment of the present invention is a method of designing a transmission line portion coupled between a transmission unit and a receiving unit, and transmitting a signal from the transmission unit to the receiving unit. Also, one-data-width distance is obtained by converting one-data-width interval, which is corresponding to a sampling period of an equalizer provided in one of the transmission unit and the receiving unit, to a distance. Further, a first reflection source for reflecting the signal is arranged at a position of the transmission line portion, where is corresponding to a ½-data-width distance corresponding to a half of the one-data-width distance. Here, the position corresponds to a grid point where a row grid line drawn on a screen used in the designing method and a column grid line drawn on the screen intersect with each other.

公开(公告)号：US20210233886A1

公开(公告)日：2021-07-29

申请号：US17108325

申请日：2020-12-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryuichi OIKAWA

IPC: H01L23/00

Abstract: A semiconductor device comprises two memory chips, one control chip controlling each memory chip, a signal transmission path through which a signal transmission between the control chip and each memory chip is performed, and a capacitance coupled onto the signal transmission path. Also, the capacitance (capacitor element) is larger than each parasitic capacitance parasitic on each chip. Accordingly, it is possible to perform the signal transmission of the semiconductor device at high speed.

公开(公告)号：US20180367186A1

公开(公告)日：2018-12-20

申请号：US16110113

申请日：2018-08-23

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA

IPC: H04B3/18 ,  H03K5/159 ,  H01L23/498 ,  H01L25/10 ,  H03K19/20 ,  H04L25/08 ,  H04L25/02 ,  H01L23/31

Abstract: The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes waveform of a signal at the end of the signal line.

公开(公告)号：US20180183411A1

公开(公告)日：2018-06-28

申请号：US15812831

申请日：2017-11-14

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Wataru Shiroi

IPC: H03H11/28 ,  H01L25/18 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L23/50

CPC classification number: H03H11/28 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5386 ,  H01L23/647 ,  H01L25/18

Abstract: To provide an inexpensive semiconductor device capable of suppressing the influence by crosstalk. A semiconductor device includes a signal wiring disposed in an organic interposer, an output circuit which is coupled to a first end of the signal wiring and which sets an impedance so as to generate a reflected wave antiphase to a waveform transmitted to the first end and periodically outputs data, and an input circuit which is coupled to a second end of the signal wiring and sets an impedance so as to generate a reflected wave of the same phase as a waveform transmitted to the second end. An average delay of the signal wiring is set to be 1/integer of 2 or more relative to a half of a cycle of the data. A difference between the maximum and minimum values of a delay of a signal at each of other signal wirings disposed in the organic interposer is set to be not greater than the average delay.

公开(公告)号：US20160218083A1

公开(公告)日：2016-07-28

申请号：US14967463

申请日：2015-12-14

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Ryuichi OIKAWA ,  Kenichi KUBOYAMA

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3025 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.

Abstract translation: 为了提高耦合在半导体芯片之间的插入器的信号传输的可靠性。 在设置在插入件的第一布线层中的信号线的两个相邻侧上设置参考电位布线和参考电位布线。 此外，在设置在插入器的第二布线层中的信号线的两个相邻侧上设置参考电位布线和参考电位布线。 此外，信号布线和信号布线在平面图中彼此交叉。 第一布线层的参考电位布线和第二布线层的参考电位布线在其交叉部分的周围彼此耦合。