公开(公告)号：US20180331197A1

公开(公告)日：2018-11-15

申请号：US16027135

申请日：2018-07-03

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: H01L29/49 ,  H01L29/06 ,  H01L27/12 ,  H01L29/51 ,  H01L21/84

CPC classification number: H01L29/4933 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0607 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/78621 ,  H01L29/78654

Abstract: While increasing a threshold voltage of a MOSFET configuring a CMOS, electric power saving of elements is achieved by suppressing excessive increase in the threshold voltage, and occurrence of performance variation among the elements is suppressed. A gate electrode of an NMOS is made of a P-type semiconductor film, a high-permittivity film is provided in a gate insulating film of the NMOS, and an impurity is prevented from being introduced into a channel region of the NMOS. Moreover, a high-permittivity film is provided also in a gate insulating film of a PMOS.

公开(公告)号：US20170294513A1

公开(公告)日：2017-10-12

申请号：US15628925

申请日：2017-06-21

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/74 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20170287795A1

公开(公告)日：2017-10-05

申请号：US15630725

申请日：2017-06-22

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Tetsuya YOSHIDA ,  Koetsu SAWAI

IPC: H01L21/66 ,  H01L21/265 ,  H01L21/768 ,  G01R31/307 ,  H01L23/535 ,  H01L23/544 ,  H01L27/11 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L22/32 ,  G01R31/307 ,  H01L21/26513 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/84 ,  H01L22/12 ,  H01L22/30 ,  H01L22/34 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/544 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection.

公开(公告)号：US20160064416A1

公开(公告)日：2016-03-03

申请号：US14924527

申请日：2015-10-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki MAKIYAMA ,  Yoshiki YAMAMOTO

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L27/1207 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42356 ,  H01L29/66545

Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.

公开(公告)号：US20240274670A1

公开(公告)日：2024-08-15

申请号：US18642509

申请日：2024-04-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/74 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1083 ,  H01L21/265 ,  H01L21/74 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/41783 ,  H01L29/4238 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/66757 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7824 ,  H01L29/7833 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78651 ,  H01L29/78654

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20200013857A1

公开(公告)日：2020-01-09

申请号：US16575836

申请日：2019-09-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20180294285A1

公开(公告)日：2018-10-11

申请号：US16005615

申请日：2018-06-11

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/265 ,  H01L29/10 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L27/1207 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/1083

Abstract: A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.

公开(公告)号：US20180083044A1

公开(公告)日：2018-03-22

申请号：US15679047

申请日：2017-08-16

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/311 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L27/1207 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/1083

Abstract: A substrate in which an insulating layer, a semiconductor layer and an insulating film are stacked on a semiconductor substrate and an element isolation region is embedded in a trench is prepared. After the insulating film in a bulk region is removed by dry etching and the semiconductor layer in the bulk region is removed by dry etching, the insulating layer in the bulk region is thinned by dry etching. A first semiconductor region is formed in the semiconductor substrate in a SOI region by ion implantation, and a second semiconductor region is formed in the semiconductor substrate in the bulk region by ion implantation. Then, the insulating film in the SOI region and the insulating layer in the bulk region are removed by wet etching. Thereafter, a first transistor is formed on the semiconductor layer in the SOI region and a second transistor is formed on the semiconductor substrate in the bulk region.

公开(公告)号：US20170330885A1

公开(公告)日：2017-11-16

申请号：US15667505

申请日：2017-08-02

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: H01L27/11 ,  H01L29/06 ,  G11C11/412 ,  H01L23/528 ,  G11C11/419 ,  H01L27/12

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0692

Abstract: A semiconductor device, including: a semiconductor substrate having a first well region; an insulating layer formed on a first portion of the semiconductor substrate, and contacted with the first well region; a semiconductor layer formed on the insulating layer; an element isolation region reaching to an inside of the first well region, in a cross-sectional view; a first gate electrode layer formed on a first portion of the semiconductor layer via a first gate insulating film; a second gate electrode layer formed on both a second portion of the semiconductor layer via a second gate insulating film and a first portion of the element isolation region; an interlayer insulating film covering the first gate electrode layer, the second gate electrode layer and a second portion of the element isolation region; a first plug conductor layer formed in the interlayer insulating film.

公开(公告)号：US20170140812A1

公开(公告)日：2017-05-18

申请号：US15264450

申请日：2016-09-13

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO

IPC: G11C11/419 ,  H01L27/12 ,  H01L27/11 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0692

Abstract: A semiconductor device with reduced power consumption. The device includes: an n-type well region overlying the main surface of a semiconductor substrate; an element isolation region overlying the main surface; a first and a second active region located in the n-type well region and surrounded by the element isolation region; an insulating film overlying the main surface in the first active region; a semiconductor layer overlying the insulating film; a gate electrode layer overlying the semiconductor layer through a gate insulating film; a p-type source and a drain region formed in the semiconductor layer at both ends of the gate electrode layer; a dummy gate electrode layer overlying the semiconductor layer through the gate insulating film; an n-type semiconductor region overlying an n-type well region surface in the second active region; and a power supply wiring coupled with the n-type semiconductor region. The dummy gate electrode layer is electrically floating.