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公开(公告)号：US09478290B1
公开(公告)日：2016-10-25
申请号：US14938394
申请日：2015-11-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Kyung-Hwa Kang , Dae-Seok Byeon , Chi-Weon Yoon
CPC classification number: G11C16/0483 , G11C7/14 , G11C8/14 , G11C16/08 , G11C16/26 , G11C16/3427 , H01L27/11575 , H01L27/11582
Abstract: A memory device is provided as follows. A memory cell array includes strings including first and second strings. Each string includes a ground selection transistor and cell transistors. First and second ground selection lines are connected to a gate of a first ground selection transistor of the first string and a gate of a second ground selection transistor of the second string, respectively. First and second cell gate lines are connected to a gate of a first cell transistor of the first string and a gate of a second cell transistor of the second string, respectively. A first interconnection unit electrically connects a first portion of the first cell gate line to a first portion of the second cell gate line. A second interconnection unit electrically connects a second portion of the first cell gate line to a second portion of the second cell gate line.
Abstract translation: 如下提供存储器件。 存储单元阵列包括包括第一和第二串的串。 每个串包括接地选择晶体管和单元晶体管。 第一和第二接地选择线分别连接到第一串的第一接地选择晶体管的栅极和第二串的第二接地选择晶体管的栅极。 第一和第二单元栅极线分别连接到第一串的第一单元晶体管的栅极和第二串的第二单元晶体管的栅极。 第一互连单元将第一单元栅极线的第一部分电连接到第二单元栅极线的第一部分。 第二互连单元将第一单元栅极线的第二部分电连接到第二单元栅极线的第二部分。
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12.发明授权Non-volatile memory device and method for programming the device, and memory system 有权用于编程器件和存储器系统的非易失性存储器件和方法公开(公告)号：US08693247B2
公开(公告)日：2014-04-08
申请号：US13919127
申请日：2013-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chi-Weon Yoon , Dong-Hyuk Chae , Sang-Wan Nam , Sung-Won Yun
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/3418
Abstract: A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.
Abstract translation: 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。
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13.发明授权Resistive memory device having memory cell arrays with multiple stack layers and bad-region managing circuit and method for managing short failure 有权具有具有多个堆叠层的存储单元阵列和不良区域管理电路的电阻式存储器件以及用于管理短路故障的方法公开(公告)号：US09570200B2
公开(公告)日：2017-02-14
申请号：US14743521
申请日：2015-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Yong-Kyu Lee , Hyun-Kook Park
CPC classification number: G11C29/76 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1695 , G11C13/0002 , G11C13/0023 , G11C13/0059 , G11C13/0064 , G11C13/0069 , G11C29/808 , G11C2029/4402 , G11C2213/71
Abstract: A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
Abstract translation: 电阻式存储器件包括存储单元阵列，其包括沿垂直方向堆叠的多个存储层。 多个存储层中的每一个包括设置在多个第一线和多条第二线彼此交叉的区域中的多个存储单元。 不良区域管理单元将包括来自多个存储器单元中的不良单元和至少一个第二存储器层的第一存储器层定义为不良区域。
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Patent Agency Ranking
公开(公告)号：US09472282B2
公开(公告)日：2016-10-18
申请号：US14979947
申请日：2015-12-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Yeong-Taek Lee , Dae-Seok Byeon , Chi-Weon Yoon
CPC classification number: G11C13/0069 , G11C5/063 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0064 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
Abstract: A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.
Abstract translation: 电阻式存储器件包括存储单元阵列，该存储单元阵列具有分别布置在多个第一信号线和多个第二信号线彼此交叉的区域上的多个电阻存储单元。 写入电路连接到从多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线，并向所选存储单元提供脉冲。 电压检测器检测所选择的第一信号线和写入电路之间的连接节点处的节点电压。 电压产生电路产生分别施加到从多个存储单元中连接到未选择的存储单元的未选择的第一和第二信号线的第一禁止电压和第二禁止电压，并且基于 检测到的节点电压。
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15.发明授权Resistive memory device and method of operating the same to reduce leakage current 有权电阻式存储器件及其操作方法，以减少漏电流公开(公告)号：US09361974B2
公开(公告)日：2016-06-07
申请号：US14683269
申请日：2015-04-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Hyun-Kook Park , Hyo-Jin Kwon
CPC classification number: G11C13/0023 , G11C13/0033 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/0078
Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.
Abstract translation: 一种操作存储器件的方法包括从多个第一信号线中确定流过所选择的第一信号线的工作电流的值，所述第一信号线被施加选择电压; 将存储单元阵列划分为n个块，n是大于1的整数，基于工作电流的值; 以及将对应于n个块的具有不同电压电平的抑制电压施加到包括在n个块中的未选择的第二信号线。 每个未选择的第二信号线是由于流过所选择的第一信号线的工作电流和由未选择的第二信号线和所选择的第一信号线寻址的存储器单元而引起的漏电流可能流过的通路。
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公开(公告)号：US09799404B2
公开(公告)日：2017-10-24
申请号：US15357291
申请日：2016-11-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
IPC: G11C11/34 , G11C16/04 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/06 , G11C16/34 , G11C16/10 , H01L27/11582 , G11C16/12
CPC classification number: G06F3/0619 , G06F3/061 , G06F3/0644 , G06F3/0655 , G06F3/0688 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/3459 , H01L27/11582
Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
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公开(公告)号：US09552878B2
公开(公告)日：2017-01-24
申请号：US15166679
申请日：2016-05-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/1675 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0071 , G11C2013/0083 , G11C2013/0092
Abstract: A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
Abstract translation: 操作存储器件的方法包括： 通过在连接到所选存储单元的第一信号线上施加第一电压并将第二电压施加到在第一设定写入间隔期间连接到所选存储单元的第二信号线，将预写电压施加到所选择的存储单元，其中 所述第一电压的电平高于所述第二电压的电平，然后通过施加具有低于所述第一电压的电平的电平的第三电压并高于所述第一电压的电平而对所选择的存储单元施加写入电压 在第二设定写入间隔期间到第一信号线的第二电压。
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公开(公告)号：US09514827B1
公开(公告)日：2016-12-06
申请号：US15018925
申请日：2016-02-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
CPC classification number: G06F3/0619 , G06F3/061 , G06F3/0644 , G06F3/0655 , G06F3/0688 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/3459 , H01L27/11582
Abstract: A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.
Abstract translation: 如下提供存储器件。 存储单元区域包括多个块，每个块包括多个NAND串。 控制逻辑基于相对于存储器单元区域的第一边缘的第一距离的较小距离和相对于存储器单元区域的第二边缘的第二距离，将多个块划分为多个块区域，以及 使用用于该操作的多个偏置操作参数组来控制在存储单元区域上执行的操作。 每个偏差集合与块区域之一相关联。
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