-
公开(公告)号：US11450684B2
公开(公告)日：2022-09-20
申请号：US17007141
申请日：2020-08-31
发明人： Woosung Yang , Byungjin Lee , Bumkyu Kang , Joonsung Lim
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L27/1157 , H01L27/11519 , H01L23/00 , H01L27/11556 , H01L27/11526 , G11C7/18 , H01L23/522 , H01L27/11524
摘要： A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.
-
公开(公告)号：US20220173060A1
公开(公告)日：2022-06-02
申请号：US17470644
申请日：2021-09-09
发明人： Jaeho Ahn , Jiwon Kim , Sungmin Hwang , Joonsung Lim , Sukkang Sung
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18
摘要： A nonvolatile memory device and a data storage system including the same are provided. The nonvolatile memory device includes: a first structure including at least one first memory plane; and a second structure bonded to the first structure and including at least one second memory plane, wherein the number of the at least one first memory plane included in the first structure is different from the number of the at least one second memory plane included in the second structure.
-
公开(公告)号：US20220157838A1
公开(公告)日：2022-05-19
申请号：US17467568
申请日：2021-09-07
发明人： Jaeho Ahn , Jiwon Kim , Sungmin Hwang , Joonsung Lim , Sukkang Sung
IPC分类号： H01L27/11524 , H01L27/11519 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L23/522 , H01L23/528
摘要： A semiconductor device and a data storage system including the same, the semiconductor device including: a first structure including a peripheral circuit; and a second structure, including: a pattern structure; an upper insulating layer; a stack structure between the first structure and the pattern structure and including first and second stack portions spaced apart from each other, the first and second stack portions respectively including horizontal conductive layers and interlayer insulating layers alternately stacked; separation structures penetrating through the stack structure; memory vertical structures penetrating through the first stack portion; and a contact structure penetrating through the second stack portion, the pattern structure, and the upper insulating layer, wherein the contact structure includes a lower contact plug penetrating through at least the second stack portion and an upper contact plug contacting the lower contact plug and extending upwardly to penetrate through the pattern structure and the upper insulating layer.
-
公开(公告)号：US12057421B2
公开(公告)日：2024-08-06
申请号：US17470644
申请日：2021-09-09
发明人： Jaeho Ahn , Jiwon Kim , Sungmin Hwang , Joonsung Lim , Sukkang Sung
IPC分类号： H01L25/065 , H01L23/00 , H01L25/18
CPC分类号： H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要： A nonvolatile memory device and a data storage system including the same are provided. The nonvolatile memory device includes: a first structure including at least one first memory plane; and a second structure bonded to the first structure and including at least one second memory plane, wherein the number of the at least one first memory plane included in the first structure is different from the number of the at least one second memory plane included in the second structure.
-
公开(公告)号：US11967574B2
公开(公告)日：2024-04-23
申请号：US17460873
申请日：2021-08-30
发明人： Sungmin Hwang , Jiwon Kim , Jaeho Ahn , Joonsung Lim , Sukkang Sung
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
CPC分类号： H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
摘要： A memory device including a first structure; and a second structure on the first structure, wherein the first structure includes a first substrate; a peripheral circuit on the first substrate; a first insulating layer covering the first substrate and the peripheral circuit; and a first bonding pad on the first insulating layer, the second structure includes a second substrate; a memory cell array on a first surface of the second substrate; a second insulating layer covering the first surface of the second substrate and the memory cell array; a conductive pattern at least partially recessed from a second surface of the second substrate; and a second bonding pad on the second insulating layer, the first bonding pad is in contact with the second bonding pad, and the conductive pattern is spaced apart from the second insulating layer.
-
公开(公告)号：US11955470B2
公开(公告)日：2024-04-09
申请号：US17229062
申请日：2021-04-13
发明人： Jiwon Kim , Jaeho Ahn , Sungmin Hwang , Joonsung Lim , Sukkang Sung
IPC分类号： H01L23/00 , H01L25/18 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40
CPC分类号： H01L25/18 , H01L24/08 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , H01L2224/08147 , H01L2924/1431 , H01L2924/1438
摘要： A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.
-
公开(公告)号：US11935597B2
公开(公告)日：2024-03-19
申请号：US17523337
申请日：2021-11-10
发明人： Jaeho Ahn , Jiwon Kim , Sungmin Hwang , Joonsung Lim , Sukkang Sung
IPC分类号： G11C16/04 , G11C16/10 , G11C16/26 , H01L23/48 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
CPC分类号： G11C16/10 , G11C16/26 , H01L23/481 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
摘要： A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.
-
公开(公告)号：US11901321B2
公开(公告)日：2024-02-13
申请号：US17854287
申请日：2022-06-30
发明人： Eun Chu Oh , Junyeong Seok , Younggul Song , Byungchul Jang , Joonsung Lim
IPC分类号： H01L23/00 , H01L25/065 , H01L25/18 , G06F11/10 , H01L25/00 , G11C7/10 , H10B41/20 , H10B41/40 , H10B41/50 , H10B43/20 , H10B43/40 , H10B43/50
CPC分类号： H01L24/08 , G06F11/1008 , G06F11/1048 , G11C7/10 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/20 , H10B41/40 , H10B41/50 , H10B43/20 , H10B43/40 , H10B43/50 , H01L2224/0603 , H01L2224/08145 , H01L2225/06524 , H01L2225/06541 , H01L2924/1431 , H01L2924/14511
摘要： A three-dimensional (3D) storage device using wafer-to-wafer bonding is disclosed. In the storage device, a first chip including a peripheral circuit region including a first control logic circuit configured to control operation modes of a nonvolatile memory (NVM) device is wafer-bonded with a second chip including 3D arrays of NVM cells, and a memory controller includes a third chip including a control circuit region. The control circuit region of the third chip includes a second control logic circuit associated with operation conditions of the NVM device, and the second control logic circuit includes a serializer/deserializer (SERDES) interface configured to share random access memory (RAM) in the memory controller and transmit and receive data to and from the NVM device.
-
公开(公告)号：US20220399369A1
公开(公告)日：2022-12-15
申请号：US17743738
申请日：2022-05-13
发明人： Yonghoon Son , Junhyoung Kim , Joonsung Lim
IPC分类号： H01L27/11582 , H01L23/522 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573
摘要： A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and extending by different lengths in a second direction on the second region to have pad regions in which upper surfaces thereof are exposed, channel structures penetrating the gate electrodes, extending in the first direction, and respectively including a channel layer, on the first region, contact plugs penetrating the pad regions of the gate electrodes and extending in the first direction, and contact insulating layers surrounding the contact plugs. The gate electrodes have side surfaces protruding further toward the contact plugs in the pad regions than ones of the gate electrodes therebelow.
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.022 秒)
