公开(公告)号：US10157676B2

公开(公告)日：2018-12-18

申请号：US15627738

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Yingda Dong ,  Jiahui Yuan ,  Charles Kwong

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C16/30 ,  G11C16/24 ,  G11C16/10 ,  G11C7/04 ,  G11C11/56 ,  G11C16/20 ,  G11C29/02 ,  G11C29/42

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. Countermeasures are provided for a first read situation in which a memory is read after a power on event or after a long delay since a last read. Read voltages of lower or higher programmed data states are set according to a positive or negative temperature coefficient (Tco), respectively. Read voltages for error recovery can be set similarly. In another aspect, a wait period between a dummy voltage and a read voltage is a function of temperature. In another aspect, word line voltages of unselected blocks are set according to a negative Tco. In another aspect, pass voltages are set based on a Tco for each programmed data state.

公开(公告)号：US10121552B1

公开(公告)日：2018-11-06

申请号：US15495178

申请日：2017-04-24

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Liang Pang ,  Yingda Dong ,  Ching-Huang Lu ,  Nan Lu ,  Hong-Yan Chen

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C16/16 ,  G11C16/32 ,  G11C16/08

Abstract: A memory device and associated techniques to reduce charge loss of memory cells. In one aspect, a charge loss countermeasure is performed if a word line selected for programming is adjacent to a dummy word line. The countermeasure can involve programming the dummy memory cells through injection disturb. In one approach, the timing is adjusted for the voltages on the selected word line and the dummy word line at the end of a program voltage. The selected word line voltage can be decreased more quickly, or the dummy word line voltage can be decreased more slowly. The decrease of the dummy word line voltage can also be delayed. Another approach involves elevating the bit line voltage during the decrease of the selected word line voltage. The bit line voltage can be a function of the assigned data state of a selected cell.

公开(公告)号：US10068657B1

公开(公告)日：2018-09-04

申请号：US15430299

申请日：2017-02-10

Applicant: SanDisk Technologies LLC

Inventor： Xuehong Yu ,  Liang Pang ,  Yingda Dong

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device and associated techniques adjust voltage ramping times optimally for each block or sub-block of memory cells to account for fabrication variations. The widths of word lines and select gate lines can vary in different sub-blocks due to misalignments in the fabrication process. The resistance and voltage settling times vary based on the widths. In one aspect, a shortest acceptable ramp down period is determined for a select gate line. This period avoids excessive read errors. A corresponding shortest acceptable word line voltage ramping period is then determined for each sub-block. A pattern in the ramp down periods can be detected among the tested sub-blocks or blocks and used to set ramp down periods in other sub-blocks or blocks. The overall time for a programming or read operation is therefore minimized.

公开(公告)号：US09812462B1

公开(公告)日：2017-11-07

申请号：US15175304

申请日：2016-06-07

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Ashish Baraskar ,  Yanli Zhang ,  Yingda Dong

IPC: H01L29/792 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7926

Abstract: Techniques are provided for fabricating a memory device in which the memory cells have a uniform program and erase speed. In one aspect, a memory device is provided with memory holes having diameters which become progressively smaller as a distance between the memory holes and a local interconnect become progressively larger. In another aspect, a fabrication process is provided for such a memory device. The memory holes which are relatively closer to the local interconnect have a relatively thinner blocking oxide layer due to etching used to remove a sacrificial material of the control gate layers. The increased diameter compensates for the thinner blocking oxide layer.

公开(公告)号：US09748266B1

公开(公告)日：2017-08-29

申请号：US15215080

申请日：2016-07-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Yanli Zhang ,  Liang Pang ,  Ching-Huang Lu ,  Matthias Baenninger ,  Yingda Dong

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/28282 ,  H01L27/1157

Abstract: A gate dielectric layer including a tunneling gate dielectric layer, a charge trapping gate dielectric layer, and a cap gate dielectric layer is formed on a horizontal semiconductor channel. An alternating stack of insulating layers and spacer material layers is formed over the gate dielectric layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conducive layers. Memory stack structures are formed through the alternating stack and the gate dielectric layer. Electrical charges can be injected into the charge trapping gate dielectric layer from the horizontal semiconductor channel to program the threshold voltage of a select field effect transistor employing a bottommost electrically conductive layer as a select gate electrode. The programmable threshold voltage can be advantageously employed to provide enhanced electrical isolation among word lines.

公开(公告)号：US09715937B1

公开(公告)日：2017-07-25

申请号：US15182853

申请日：2016-06-15

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Yingda Dong ,  Jiahui Yuan ,  Charles Kwong

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C16/30 ,  G11C16/24 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/20 ,  G11C16/24 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C2211/563

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. Countermeasures are provided for a first read situation in which a memory is read after a power on event or after a long delay since a last read. Read voltages of lower or higher programmed data states are set according to a positive or negative temperature coefficient (Tco), respectively. Read voltages for error recovery can be set similarly. In another aspect, a wait period between a dummy voltage and a read voltage is a function of temperature. In another aspect, word line voltages of unselected blocks are set according to a negative Tco. In another aspect, pass voltages are set based on a Tco for each programmed data state.

公开(公告)号：US09620233B1

公开(公告)日：2017-04-11

申请号：US15198205

申请日：2016-06-30

Applicant: SanDisk Technologies LLC

Inventor： Yingda Dong ,  Xuehong Yu ,  Liang Pang

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/32 ,  G11C16/3427 ,  H01L27/11582

Abstract: Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. In one aspect, a read pass voltage is discharged in a manner that purges residual electrons from a memory string channel after a sensing operation. A control circuit may begin to discharge the read pass voltage from memory cell control gates at different strategic times in order to provide a path for residual electrons to leave the channel. Because residual electrons have been purged from the channel, no or very few electrons will be trapped in shallow interface traps of the memory cell if the word line voltage does creep up following sensing. Thus, the word line voltage may still creep up after the sensing operation without changing a threshold voltage of the memory cell.

公开(公告)号：US10372536B2

公开(公告)日：2019-08-06

申请号：US15921165

申请日：2018-03-14

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G11C16/28 ,  G06F11/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G11C11/56 ,  G11C16/32

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

公开(公告)号：US20180203763A1

公开(公告)日：2018-07-19

申请号：US15921184

申请日：2018-03-14

Applicant: SanDisk Technologies LLC

Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

CPC classification number: G06F11/1068 ,  G06F11/08 ,  G06F11/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C29/52 ,  G11C2207/2281

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A memory cell is sensed by discharging a sense node into a bit line and detecting an amount of discharge at two sense times relative to a trip voltage. A bit of data is stored in first and second latches based on the two sense times, to provide first and second pages of data. The pages are evaluated using parity check equations and one of the pages which satisfies the most equations is selected. In another option, word line voltages are grounded and then floated to prevent coupling up of the word line. A weak pulldown to ground can gradually discharge a coupled up voltage of the word lines.

公开(公告)号：US20180190667A1

公开(公告)日：2018-07-05

申请号：US15906317

申请日：2018-02-27

Applicant: SanDisk Technologies LLC

Inventor： Liang Pang ,  Jayavel Pachamuthu ,  Yingda Dong

IPC: H01L27/11519 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/02 ,  H01L27/11556 ,  H01L27/11524

CPC classification number: H01L27/11519 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833

Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.