公开(公告)号：US10950629B2

公开(公告)日：2021-03-16

申请号：US16877535

申请日：2020-05-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Fei Zhou ,  Senaka Krishna Kanakamedala ,  Yao-Sheng Lee

IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11556

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.

公开(公告)号：US10916504B2

公开(公告)日：2021-02-09

申请号：US16441439

申请日：2019-06-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke Mukae ,  Naoki Takeguchi ,  Kensuke Yamaguchi ,  Raghuveer S. Makala ,  Yujin Terasawa

IPC: H01L21/28 ,  H01L29/49 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/768

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.

公开(公告)号：US10438964B2

公开(公告)日：2019-10-08

申请号：US15633131

申请日：2017-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Senaka Krishna Kanakamedala ,  Yanli Zhang ,  Yao-Sheng Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/423 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/08 ,  H01L21/28 ,  H01L21/311

Abstract: A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.

公开(公告)号：US20190259946A1

公开(公告)日：2019-08-22

申请号：US15901633

申请日：2018-02-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Senaka Kanakamedala ,  Yao-Sheng Lee

IPC: H01L45/00 ,  H01L27/24

Abstract: First stacked rail structures including a first conductive rail, a selector rail, and a sacrificial material rail and separated by first trenches are formed over a substrate. First dielectric isolation structures are formed in the first trenches. Second trenches are formed, which divides the first stacked rail structures above the first conductive rails. Second dielectric isolation structures in the second trenches. Pillar structures are formed, which include a respective vertical stack of a selector element and a sacrificial material pillar. The sacrificial material pillars are replaced with phase change memory material pillars by a damascene method that deposits and planarizes a phase change memory material. Second conductive rails are formed over the phase change memory material pillars. Sidewalls of the phase change memory material pillars are not subjected to etch damage, thereby enhancing electrical characteristics of the phase change memory material pillars.

公开(公告)号：US10381559B1

公开(公告)日：2019-08-13

申请号：US16002169

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Christopher J. Petti ,  Rahul Sharangpani ,  Adarsh Rajashekhar ,  Seung-Yeul Yang

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.

公开(公告)号：US20190139973A1

公开(公告)日：2019-05-09

申请号：US15804692

申请日：2017-11-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Adarsh Rajashekhar

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/8239 ,  H01L21/8234

Abstract: A memory opening is formed through an alternating stack of insulating layers and sacrificial material layers located over a substrate. Annular recesses are formed around the memory opening by laterally recessing the sacrificial material layers with respect to the insulating layers. Annular metal portions are formed over recessed sidewalls of the sacrificial material layers within each of the annular recesses by a selective deposition process. Annular backside blocking dielectrics are formed selectively on inner sidewalls of the annular metal portions employing a layer of a self-assembly material that covers surfaces of the insulating layers and inhibits deposition of a dielectric material thereupon. A memory stack structure is formed in the memory opening, and the sacrificial material layers are replaced with electrically conductive layers. The annular backside blocking dielectrics provide electrical isolation for the annular metal portions, which function as control gate electrodes.

公开(公告)号：US10115730B1

公开(公告)日：2018-10-30

申请号：US15626766

申请日：2017-06-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish Baraskar ,  Naohiro Hosoda ,  Yanli Zhang ,  Raghuveer S. Makala ,  Hiroyuki Tanaka ,  Ryo Nakamura ,  Tadashi Nakamura

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/265

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening and contacting a top surface of the semiconductor surface, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure.

公开(公告)号：US20180090373A1

公开(公告)日：2018-03-29

申请号：US15830838

申请日：2017-12-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar ,  Senaka Krishna Kanakamedala ,  Fumitaka Amano ,  Genta Mizuno

IPC: H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L21/285

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

公开(公告)号：US09893081B1

公开(公告)日：2018-02-13

申请号：US15231205

申请日：2016-08-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka Kanakamedala ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Somesh Peri ,  Yao-Sheng Lee

IPC: H01L29/792 ,  H01L27/115 ,  H01L21/768 ,  H01L29/788 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11556 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. Backside recesses are formed by removing the sacrificial material layers and surface portions of the blocking dielectric to form backside recesses including vertically expanded end portions. Electrically conductive layers are formed within the backside recesses. Each of the electrically conductive layers is a control gate electrode which includes a uniform thickness portion and a ridged end portion having a greater vertical extent than the uniform thickness region. The ridged end portion laterally surrounds the memory stack structure and provides a longer gate length for the control gate electrodes for the memory stack structure.

公开(公告)号：US09842857B2

公开(公告)日：2017-12-12

申请号：US15440365

申请日：2017-02-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Sateesh Koka ,  Raghuveer S. Makala ,  Srikanth Ranganathan ,  Mark Juanitas ,  Johann Alsmeier

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/02321 ,  H01L21/02356 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31155 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/7883

Abstract: A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.