中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

58 records (took 0.017 seconds)

    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
    12.
    发明授权
    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units 有权

    公开(公告)号：US11024561B2

    公开(公告)日：2021-06-01

    申请号：US16885640

    申请日：2020-05-28

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

    Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units
    15.
    发明申请
    Semiconductor Device and Method of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units 审中-公开

    公开(公告)号：US20200294890A1

    公开(公告)日：2020-09-17

    申请号：US16885640

    申请日：2020-05-28

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

    Semiconductor device and method of forming MEMS package
    16.
    发明授权
    Semiconductor device and method of forming MEMS package 有权

    公开(公告)号：US10730745B2

    公开(公告)日：2020-08-04

    申请号：US15610997

    申请日：2017-06-01

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Il Kwon Shim

    IPC: H01L23/48 ,  B81B7/00

    Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

    Semiconductor Device and Method of Using a Standardized Carrier to Form Embedded Wafer Level Chip Scale Packages
    17.
    发明申请
    Semiconductor Device and Method of Using a Standardized Carrier to Form Embedded Wafer Level Chip Scale Packages 审中-公开

    公开(公告)号：US20200227383A1

    公开(公告)日：2020-07-16

    申请号：US16827363

    申请日：2020-03-23

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Byung Joon Han ,  Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

    Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die.

    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
    18.
    发明授权
    Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units 有权

    公开(公告)号：US10707150B2

    公开(公告)日：2020-07-07

    申请号：US16030668

    申请日：2018-07-09

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

    Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

Patent Agency Ranking