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34 条记录 (耗时 0.016 秒)

    Capacitance multiplier and loop filter noise reduction in a PLL
    13.
    发明授权
    Capacitance multiplier and loop filter noise reduction in a PLL 有权
    PLL中的电容乘法器和环路滤波器降噪

    公开(公告)号：US09294106B2

    公开(公告)日：2016-03-22

    申请号：US14323794

    申请日：2014-07-03

    申请人： STMicroelectronics International N.V.

    发明人： Abhirup Lahiri ,  Nitin Gupta

    IPC分类号： H03L7/06 ,  H03L7/089 ,  H03L7/093

    CPC分类号： H03L7/093 ,  H03L7/089

    摘要： According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path.

    摘要翻译： 根据实施例，电路包括被配置为在第一节点处产生第一电流的第一电荷泵，被配置为在第二节点处产生第二电流的第二电荷泵，耦合在第一和第二节点之间的环路滤波器， 环路滤波器，包括耦合到第一节点的第一滤波器路径，耦合到第二节点的第二滤波器路径以及插在第一和第二滤波器路径之间的隔离缓冲器。 第二节点处的第二个电流与第一节点处的第一个电流不同。 该电路还包括一个振荡器，被配置为对第一滤波器路径的输出施加第一增益，并将第二增益应用于第二滤波器路径的输出。

    Locked loop circuit with reference signal provided by un-trimmed oscillator
    14.
    发明授权
    Locked loop circuit with reference signal provided by un-trimmed oscillator 有权

    公开(公告)号：US10862487B2

    公开(公告)日：2020-12-08

    申请号：US16674207

    申请日：2019-11-05

    申请人： STMicroelectronics International N.V.

    发明人： Anand Kumar ,  Nitin Gupta ,  Nitin Jain

    IPC分类号： H03L1/00 ,  H03L7/183 ,  H03L7/087 ,  H03L7/085

    摘要： A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

    Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop
    16.
    发明授权
    Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop 有权

    公开(公告)号：US10566980B2

    公开(公告)日：2020-02-18

    申请号：US15924584

    申请日：2018-03-19

    申请人： STMicroelectronics International N.V.

    发明人： Nitin Gupta ,  Jeet Narayan Tiwari

    IPC分类号： H03L7/07 ,  H03L7/099 ,  H03L7/095

    摘要： Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.

    DATA ON CLOCK LANE OF SOURCE SYNCHRONOUS LINKS
    17.
    发明申请
    DATA ON CLOCK LANE OF SOURCE SYNCHRONOUS LINKS 有权
    源码同步链路时钟数据

    公开(公告)号：US20170005780A1

    公开(公告)日：2017-01-05

    申请号：US14788721

    申请日：2015-06-30

    申请人： STMicroelectronics International N.V.

    发明人： Tapas Nandy ,  Nitin Gupta

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0008 ,  G06F1/10 ,  H04J3/0685 ,  H04L1/0026 ,  H04L5/00 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033 ,  H04L7/0337

    摘要： A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

    摘要翻译： 源同步数据传输系统包括数据发送装置和数据接收装置。 专用数据线将数据信号从数据传输装置传送到数据接收装置。 专用时钟线将数据传输装置的调制时钟信号传送到数据接收装置。 数据传输装置包括：时钟数据驱动器，被配置为通过调制调制时钟信号的幅度将数据编码成调制时钟信号。 因此，源同步数据传输系统的时钟线携带时钟信号和附加数据。

    ASYNCHRONOUS HIGH-SPEED PROGRAMMABLE DIVIDER
    18.
    发明申请
    ASYNCHRONOUS HIGH-SPEED PROGRAMMABLE DIVIDER 有权
    异步高速可编程分频器

    公开(公告)号：US20160315621A1

    公开(公告)日：2016-10-27

    申请号：US14691738

    申请日：2015-04-21

    申请人： STMicroelectronics International N.V.

    发明人： Jeet Narayan Tiwari ,  Nitin Gupta

    IPC分类号： H03K21/02

    CPC分类号： H03K21/026 ,  H03K21/00 ,  H03K23/00 ,  H03K23/58 ,  H03K23/667 ,  H03K23/68

    摘要： A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2N-M−1 times out of 2N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2N-M, 2N-M times, using the divider.

    摘要翻译： 本文描述了将时钟信号除以具有M个最高有效位的N位的输入信号的方法。 该方法包括使用分频器将时钟信号除以时钟信号的2N-M分频之外的输入信号2N-M-1的最高有效位。 使用分频器，将时钟信号除以时钟信号的2N-M分频之外的最高有效位和最低有效位之和。 使用分频器也可以将时钟信号除以2N-M，2N-M次。

    Automatic power switching and power harvesting in thin oxide open drain transmitter circuits, systems, and methods
    19.
    发明授权
    Automatic power switching and power harvesting in thin oxide open drain transmitter circuits, systems, and methods 有权
    薄氧化物开漏发射器电路，系统和方法中的自动功率开关和功率采集

    公开(公告)号：US09331671B2

    公开(公告)日：2016-05-03

    申请号：US14283043

    申请日：2014-05-20

    申请人： STMICROELECTRONICS INTERNATIONAL N.V.

    发明人： Nitin Gupta ,  Paramjeet Singh Sahni ,  Tapas Nandy ,  Manish Garg

    IPC分类号： H04B3/00 ,  H04L25/00 ,  H03K3/01 ,  H04N5/44 ,  H04N5/63 ,  H03K19/0185

    CPC分类号： H03K3/01 ,  H03K19/018528 ,  H04N5/44 ,  H04N5/63

    摘要： A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.

    摘要翻译： 功率收集电路包括新的发射机拓扑结构，其确保形成功率收集电路的薄氧化物晶体管的结不会经受超过最大可容忍结电压的晶体管结的电压。 补充供电电路用于在从接收器电路收集的功率不足以对发射机电路的这些组件充分供电时，向发射机电路中的组件提供补充馈电电流，这可能在耦合发射机的通信信道的高频操作期间发生 和接收器电路。 当从接收器电路收集的功率大于为发射机电路中的组件供电所需的功率时，辅助馈电电路还用于吸收分流电流。

    Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature
    20.
    发明授权
    Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature 有权
    锁相环（PLL）电路，具有过程，电压和温度的补偿带宽

    公开(公告)号：US09325324B1

    公开(公告)日：2016-04-26

    申请号：US14573002

    申请日：2014-12-17

    申请人： STMicroelectronics International N.V.

    发明人： Nitin Gupta ,  Anand Kumar ,  Abhirup Lahiri

    IPC分类号： H03L7/00 ,  H03L1/02 ,  H03L7/093 ,  H03L7/18 ,  H03L7/099 ,  H03L7/107

    CPC分类号： H03L7/099 ,  H03L1/00 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/113 ,  H03L7/18

    摘要： A phase locked loop (PLL) circuit includes a phase comparison circuit configured to compare phase of an input signal to phase of a feedback signal and generate a control signal responsive to the phase comparison and an oscillator circuit configured to generate an output signal at a frequency set by said control signal, where said feedback signal is derived from said output signal. The PLL circuit further operates in a calibration mode of operation wherein the oscillator circuit operates in a frequency locked loop mode to compare frequency of the input signal to frequency of the output signal and center a gain of the oscillator circuit across process, voltage and temperature in response to the frequency comparison. Furthermore, bias current for a charge pump within the phase comparison circuit is calibrated during calibration mode of operation to match a temperature independent reference current.

    摘要翻译： 锁相环（PLL）电路包括相位比较电路，其被配置为将输入信号的相位与反馈信号的相位进行比较，并响应于相位比较产生控制信号，以及振荡器电路，被配置为产生频率的输出信号 由所述控制信号设置，其中所述反馈信号从所述输出信号导出。 PLL电路进一步在校准操作模式下工作，其中振荡器电路以频率锁定环路模式操作，以将输入信号的频率与输出信号的频率进行比较，并将振荡器电路的增益集中在过程，电压和温度之间 响应频率比较。 此外，相位比较电路内的电荷泵的偏置电流在校准操作模式下进行校准，以匹配与温度无关的参考电流。