公开(公告)号：US10706924B2

公开(公告)日：2020-07-07

申请号：US16393115

申请日：2019-04-24

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Roberto Annunziata ,  Paola Zuliani

IPC: G11C11/00 ,  G11C13/00

Abstract: A non-volatile memory device has a circuit branch associated to a bit line connected to a memory cell. When the memory cell is read, in a precharging step, the bit line is precharged. In a characteristic shift step, the memory cell is activated, and a current source is activated to supply a shift current to the first bit line and cause the bit line to charge or discharge on the basis of the datum stored in the memory cell. In a detection step, the current source is deactivated, the memory cell is decoupled, and the bit line is coupled to an input of a comparator stage that compares the voltage on the bit line with a reference voltage to supply an output signal indicating a datum stored in the memory cell.

公开(公告)号：US20180130538A1

公开(公告)日：2018-05-10

申请号：US15862397

申请日：2018-01-04

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Salvatore Polizzi

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28 ,  G11C2207/002 ,  G11C2207/12

Abstract: A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a first bitline, associated to the memory cell, and a second bitline, has: a first circuit branch associated to the first bitline and a second circuit branch associated to the second bitline, each with a local node, coupled to which is a first dividing capacitor, and a global node, coupled to which is a second dividing capacitor; a decoder stage for coupling the local node to the first or second bitlines and coupling the global node to the local node; and a differential comparator stage supplies an output signal indicative of the datum stored; and a control unit for controlling the decoder stage, the coupling stage, and the differential comparator stage for generation of the output signal.

公开(公告)号：US09966145B2

公开(公告)日：2018-05-08

申请号：US15605708

申请日：2017-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Salvatore Polizzi ,  Giovanni Campardo

IPC: G11C16/10 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/32 ,  G11C5/14 ,  G11C8/12 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C5/145 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.

公开(公告)号：US09767907B2

公开(公告)日：2017-09-19

申请号：US15083056

申请日：2016-03-28

Applicant: STMicroelectronics S.R.L.

Inventor： Salvatore Polizzi ,  Giovanni Campardo

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C8/10

CPC classification number: G11C16/08 ,  G11C8/10 ,  G11C16/10 ,  G11C16/24

Abstract: A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address signals. A decoding module receives the pre-decoded address signals for generation on an output of decoded address signals. A driving module generates biasing signals for biasing wordlines of a memory array. The decoding module envisages a plurality of decoding stages, each of which carries out an operation of an OR logic combination between a first and a second predecoded address signal to be combined. The decoding module includes at least one first pass transistor for selectively transferring onto the output the one between the first and second predecoded address signals to be combined in a first operating condition. The decoding module includes at least one first pull-up transistor to selectively bring the output to a high state in at least one second operating condition.

公开(公告)号：US20170084334A1

公开(公告)日：2017-03-23

申请号：US15083056

申请日：2016-03-28

Applicant: STMicroelectronics S.R.L.

Inventor： Salvatore Polizzi ,  Giovanni Campardo

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C8/10 ,  G11C16/10 ,  G11C16/24

Abstract: A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address signals. A decoding module receives the pre-decoded address signals for generation on an output of decoded address signals. A driving module generates biasing signals for biasing wordlines of a memory array. The decoding module envisages a plurality of decoding stages, each of which carries out an operation of an OR logic combination between a first and a second predecoded address signal to be combined. The decoding module includes at least one first pass transistor for selectively transferring onto the output the one between the first and second predecoded address signals to be combined in a first operating condition. The decoding module includes at least one first pull-up transistor to selectively bring the output to a high state in at least one second operating condition.

公开(公告)号：US20220199900A1

公开(公告)日：2022-06-23

申请号：US17644942

申请日：2021-12-17

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Massimo Borghi

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  H01L23/528

Abstract: A phase-change memory (PCM) includes a semiconductor body housing a selection transistor; a electrical-insulation body disposed over the semiconductor body; a conductive region, extending through the electrical-insulation body, electrically coupled to the selection transistor; and a plurality of heater elements in the electrical-insulation body. Each of the plurality of heater elements include a first end in electrical contact with a respective portion of the conductive region and a second end that extends away from the conductive region. The PCM further includes a plurality of phase-change elements extending in the electrical-insulation body and including data storage regions, where each of the data storage regions being electrically and thermally coupled to one respective heater element at the second end of the respective heater element.

公开(公告)号：US20210166757A1

公开(公告)日：2021-06-03

申请号：US17099257

申请日：2020-11-16

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Massimo Borghi ,  Paola Zuliani ,  Marco Barboni

IPC: G11C13/00 ,  H01L45/00

Abstract: An embodiment phase-change memory device includes a memory array provided with a plurality of phase-change memory cells, each having a body made of phase-change material and a first state, in which the phase-change material is completely in an amorphous phase, and at least one second state, in which the phase-change material is partially in the amorphous phase and partially in a crystalline phase. A programming-pulse generator applies to the memory cells rectangular dynamic-programming pulses having an amplitude and a duration calibrated for switching the memory cells from the first state to the second state.

公开(公告)号：US20180033564A1

公开(公告)日：2018-02-01

申请号：US15470431

申请日：2017-03-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Giovanni Campardo ,  Carlo Valzasina

IPC: H01H1/00 ,  B81B7/00 ,  B81B7/04

CPC classification number: H01H1/0036 ,  B81B7/0003 ,  B81B7/007 ,  B81B7/04 ,  B81B2201/01 ,  B81B2203/0118 ,  B81B2207/01 ,  H01H1/0094 ,  H01H59/0009 ,  H01H2001/0042 ,  H01H2001/0068 ,  H01H2001/0078 ,  H01H2001/145

Abstract: A microelectromechanical device, in particular a non-volatile memory module or a relay, comprising: a mobile body including a top region and a bottom region; top electrodes facing the top region; and bottom electrodes, facing the bottom region. The mobile body is, in a resting condition, at a distance from the electrodes. The latter can be biased for generating a movement of the mobile body for causing a direct contact of the top region with the top electrodes and, in a different operating condition, a direct contact of the bottom region with the bottom electrodes. In the absence of biasing, molecular-attraction forces maintain in stable mutual contact the top region and the top electrodes or, alternatively, the bottom region and the bottom electrodes.

公开(公告)号：US09805810B1

公开(公告)日：2017-10-31

申请号：US15387397

申请日：2016-12-21

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Salvatore Polizzi

IPC: G11C7/00 ,  G11C16/28 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/14 ,  G11C7/227 ,  G11C8/08 ,  G11C8/14 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense amplifier generates a corresponding output signal representing a datum stored in a corresponding memory cell pre-charged by the first pre-charging stage. A second pre-charging stage biases the dummy word line simultaneously with the word line biased by the first pre-charging stage. The output stage includes an enable stage, which detects a state of complete pre-charging of an intermediate dummy cell.

公开(公告)号：US20250008847A1

公开(公告)日：2025-01-02

申请号：US18884913

申请日：2024-09-13

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Massimo Borghi

IPC: H10N70/20 ,  G11C13/00 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00

Abstract: A phase-change memory (PCM) includes a semiconductor body housing a selection transistor; a electrical-insulation body disposed over the semiconductor body; a conductive region, extending through the electrical-insulation body, electrically coupled to the selection transistor; and a plurality of heater elements in the electrical-insulation body. Each of the plurality of heater elements include a first end in electrical contact with a respective portion of the conductive region and a second end that extends away from the conductive region. The PCM further includes a plurality of phase-change elements extending in the electrical-insulation body and including data storage regions, where each of the data storage regions being electrically and thermally coupled to one respective heater element at the second end of the respective heater element.