公开(公告)号：US20150364546A1

公开(公告)日：2015-12-17

申请号：US14722402

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Rwik Sengupta

IPC: H01L29/10 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/775

Abstract: A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.

Abstract translation: 包括堆叠的纳米片场效应晶体管（FET）的器件可以包括衬底，衬底上的第一沟道图案，第一沟道图案上的第二沟道图案，被配置为围绕第一沟道图案的部分的栅极和部分 的第二沟道图案和第一沟道图案和第二沟道图案的相对端上的源极/漏极区域。 第一和第二通道图案可以各自包括布置在平行于基板的表面的相应水平平面中的相应的多个纳米片。 纳米片可以在相邻的纳米片之间的水平间隔距离处彼此间隔开。 第二通道图案可以与第一通道图案间隔开距离第一通道图案到第二通道图案的垂直间隔距离大于水平间隔距离。

公开(公告)号：US11983622B2

公开(公告)日：2024-05-14

申请号：US18111471

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: G06N3/065 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L29/808 ,  H10B41/30

CPC classification number: G06N3/065 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/8083 ,  H10B41/30

Abstract: A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.

公开(公告)号：US10930768B2

公开(公告)日：2021-02-23

申请号：US16282048

申请日：2019-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Borna J. Obradovic ,  Kang-ill Seo ,  Mark Stephen Rodder

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of manufacturing a field effect transistor includes forming a fin on a substrate, forming source and drain electrodes on opposite sides of the fin, forming a gate stack on a channel portion of the fin between the source and drain electrodes, forming gate spacers on extension portions of the fin on opposite sides of the gate stack, removing at least a portion of the gate spacers to expose the extension portions of the fin, and thinning the extension portions of the fin. Following the thinning of the extension portions of the fin, the channel portion of the fin has a first width and the extension portions of the fin have a second width less than the first width.

公开(公告)号：US10739186B2

公开(公告)日：2020-08-11

申请号：US15886753

申请日：2018-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Titash Rakshit

IPC: G11C7/10 ,  G11C13/00 ,  G01G23/38 ,  G06G7/16 ,  G11C11/54 ,  G06N3/063 ,  G11C11/16

Abstract: A weight cell including first and second bi-directional memory elements each configured to switch between a first resistance state and a second resistance state different than the first resistance state. A first input line is connected to a first terminal of the first bi-directional memory element, and a second input line is connected to the first terminal of the second bi-directional memory element. A first diode in forward bias connects the second terminal of the first bi-directional memory element to a first output line, a second diode in reverse bias connects the second terminal of the second bi-directional memory element to a second output line, a third diode in reverse bias connects the second terminal of the first bi-directional memory element to the second output line, and a fourth diode in forward bias connects the second terminal of the second bi-directional memory element to the first output line.

公开(公告)号：US20190385856A1

公开(公告)日：2019-12-19

申请号：US16551028

申请日：2019-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/8238 ,  H01L27/092

Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

公开(公告)号：US20190319108A1

公开(公告)日：2019-10-17

申请号：US16141767

申请日：2018-09-25

Applicant: Samsung Electronics Co., LTD.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Titash Rakshit

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/66

Abstract: A semiconductor device and method for providing a semiconductor device are described. The semiconductor device includes a channel, a gate, and a multilayer gate insulator structure between the gate and the channel. The multilayer gate insulator structure includes at least one ferroelectric layer and at least one dielectric layer. The at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling.

公开(公告)号：US20190318774A1

公开(公告)日：2019-10-17

申请号：US16142944

申请日：2018-09-26

Applicant: Samsung Electronics Co., LTD.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Ryan M. Hatcher ,  Titash Rakshit

IPC: G11C11/22

Abstract: A semiconductor memory device and method for providing the semiconductor memory device are described. The semiconductor memory device includes a ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode and a multilayer insulator structure between the first and second electrodes. The multilayer insulator structure includes at least one ferroelectric layer and at least one dielectric layer. The at least one ferroelectric layer and the at least one dielectric layer share at least one interface and have a strong polarization coupling.

公开(公告)号：US10381271B2

公开(公告)日：2019-08-13

申请号：US15997596

申请日：2018-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/66 ,  H01L27/04 ,  H01L21/84

Abstract: A field effect transistor includes a fin having a stack of nanowire-like channel regions including at least first and a second nanowire-like channel regions, source and drain electrodes on opposite sides of the fin, a dielectric separation region including a dielectric material between the first and second nanowire-like channel regions, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The dielectric separation region extending completely from a surface of the second nanowire-like channel region facing the first nanowire-like channel region to a surface of the first nanowire-like channel region facing the second nanowire-like channel region. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer of the gate stack does not extend between the first and second nanowire-like channel regions.

公开(公告)号：US10199474B2

公开(公告)日：2019-02-05

申请号：US15485188

申请日：2017-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12

Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a substrate and a fin including at least one channel region decoupled from the substrate. The FET also includes a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the channel region of the fin. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The FET also includes an oxide separation region separating the channel region of the fin from the substrate. The oxide separation region includes a dielectric material that includes a portion of the gate dielectric layer of the gate stack. The oxide separation region extends completely from a surface of the channel region facing the substrate to a surface of the substrate facing the channel region.

公开(公告)号：US20180166550A1

公开(公告)日：2018-06-14

申请号：US15485188

申请日：2017-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785 ,  H01L2029/42388

Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a substrate and a fin including at least one channel region decoupled from the substrate. The FET also includes a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the channel region of the fin. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The FET also includes an oxide separation region separating the channel region of the fin from the substrate. The oxide separation region includes a dielectric material that includes a portion of the gate dielectric layer of the gate stack. The oxide separation region extends completely from a surface of the channel region facing the substrate to a surface of the substrate facing the channel region.