公开(公告)号：US20230268441A1

公开(公告)日：2023-08-24

申请号：US18307279

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/41791 ,  H01L29/6681 ,  H01L21/823431 ,  H01L29/045

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20230268395A1

公开(公告)日：2023-08-24

申请号：US18062713

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum KIM ,  Sujin JUNG ,  Gyeom KIM ,  Dahye KIM ,  Ingyu JANG ,  Kyungbin CHUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/764 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66439

Abstract: A semiconductor device includes; a gate structure intersecting an active region, and a plurality of channel layers, extending on the substrate in a second direction, and surrounding the plurality of channel layers; a source/drain region contacting the plurality of channel layers on at least one side of the gate structure and including a first semiconductor material with first impurities having a first conductivity type; and a lower structure in contact with the active region and below the source/drain region. The lower structure includes a first layer disposed on the active region and including an insulating material; a second layer disposed on the first layer and including a second semiconductor material; with an air gap defined by the first layer and the second layer, wherein the second semiconductor material of the second layer has no conductivity type or has a second conductivity type different from the first conductivity type.

公开(公告)号：US20240413246A1

公开(公告)日：2024-12-12

申请号：US18809745

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20240304666A1

公开(公告)日：2024-09-12

申请号：US18667417

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jinbum KIM ,  Gyeom KIM ,  Hyojin KIM ,  Haejun YU ,  Seunghun LEE ,  Kyungin CHOI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.

公开(公告)号：US20240282830A1

公开(公告)日：2024-08-22

申请号：US18535421

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom KIM ,  Jinbum KIM ,  Sangmoon LEE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/4175 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate insulating layer; a gate structure extending in one direction on the substrate insulating layer; a source/drain region outside of the gate structure; and a backside contact plug below the source/drain region to have a second central axis offset from a first central axis of the source/drain region in a horizontal direction, and connected to the source/drain region, wherein the source/drain region includes a first epitaxial layer including a non-silicon element in a first concentration, and a second epitaxial layer on the first epitaxial layer and including a non-silicon element in a second concentration, higher than the first concentration, and at least a portion of an upper surface of the backside contact plug is in contact with the second epitaxial layer.

公开(公告)号：US20240145541A1

公开(公告)日：2024-05-02

申请号：US18313630

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da Hye KIM ,  Jin Bum KIM ,  Gyeom KIM ,  Young Kwang KIM ,  Kyung Bin CHUN

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction. The sheet patterns include an uppermost sheet pattern and a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction. Each of the plurality of gate structures includes a gate electrode and a gate insulating film and a source/drain pattern between adjacent ones of the plurality of gate structures. Each of inner gate structures includes a gate electrode and a gate insulating film. A semiconductor liner film includes silicon-germanium, and contacts the gate insulating film of each of the inner gate structures. A portion of the semiconductor liner film protrudes upwardly in the first direction beyond an upper surface of the uppermost sheet pattern.

公开(公告)号：US20220293730A1

公开(公告)日：2022-09-15

申请号：US17479424

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum KIM ,  Gyeom KIM ,  Hyojin KIM ,  Haejun YU ,  Seunghun LEE ,  Kyungin CHOI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap.

公开(公告)号：US20210217860A1

公开(公告)日：2021-07-15

申请号：US17141513

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong HA ,  Dongwoo KIM ,  Gyeom KIM ,  Yong Seung KIM ,  Pankwi PARK ,  Seung Hun LEE

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US20140374827A1

公开(公告)日：2014-12-25

申请号：US14259212

申请日：2014-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Chan SUH ,  Chung-Geun KOH ,  Seong-Hoon JEONG ,  Kwan-Heum LEE ,  Hwa-Sung RHEE ,  Gyeom KIM

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/66545

Abstract: A semiconductor device includes a fin type active pattern protruding above a device isolation layer, a gate electrode on the device isolation layer and intersecting the fin type active pattern, an elevated source/drain on the fin type active pattern at both sides of the gate electrode, and a fin spacer on a side wall of the fin type active pattern, the fin spacer having a low dielectric constant and being between the device isolation layer and the elevated source/drain.

Abstract translation: 半导体器件包括突出在器件隔离层上方的翅片型有源图案，器件隔离层上的栅电极并与鳍式有源图案相交，栅极电极两侧的翅片型有源图案上的升高的源极/漏极 以及在翅片型有源图案的侧壁上的翅片间隔件，翅片间隔件具有低介电常数并且位于器件隔离层和升高的源极/漏极之间。

公开(公告)号：US20240222467A1

公开(公告)日：2024-07-04

申请号：US18243251

申请日：2023-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jieun YUN ,  Sunhye HWANG ,  Gyeom KIM ,  Ji Young PARK ,  Sangmoon LEE

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/66439 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: A method of manufacturing an integrated circuit device, the method including forming a structure on a substrate, a semiconductor film and an insulating film being exposed in the structure, and selectively forming a silicon germanium layer only on the semiconductor film by using a process gas, the process gas including a disilane compound having at least two chlorine atoms, a germanium element-containing gas, and hydrogen gas.