公开(公告)号：US20170162431A1

公开(公告)日：2017-06-08

申请号：US15353984

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Jong Min BAEK ,  Myung Geun SONG ,  Woo Kyung YOU ,  Byung Kwon CHO ,  Byung Hee KIM ,  Na Ein LEE

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

公开(公告)号：US20240222453A1

公开(公告)日：2024-07-04

申请号：US18228376

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eui Bok LEE ,  Rak Hwan KIM ,  Jong Min BAEK ,  Moon Kyun SONG

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/775

Abstract: A semiconductor device includes an interlayer insulating film including a first surface and a second surface opposite to the first surface in a first direction; a source/drain pattern provided in the interlayer insulating film; a channel pattern adjacent to the source/drain pattern in a second direction and contacting the source/drain pattern; a front wiring provided on the first surface of the interlayer insulating film; a back wiring provided on the second surface of the interlayer insulating film; and a first connecting via contact and a second connecting via contact which are provided between the source/drain pattern and the back wiring and connected to the source/drain pattern.

公开(公告)号：US20220392841A1

公开(公告)日：2022-12-08

申请号：US17671088

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Deok Young JUNG ,  Jun Hyuk LIM

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device includes an etching stop film disposed on a substrate; an interlayer insulating film on the etching stop film; a first trench and a second trench which are spaced apart in a first direction, and penetrate the etching stop film and the interlayer insulating film, the first trench having a side wall that exposes the interlayer insulating film, and the second trench having a side wall that exposes the interlayer insulating film; a first spacer which covers the interlayer insulating film exposed by the side wall of the first trench and does not cover a portion of the side wall of the first trench; a second spacer which covers the interlayer insulating film exposed by the side wall of the second trench and does not cover a portion of the side wall of the second trench; a first barrier layer which extends along a side wall of the first spacer, the portion of the side wall of the first trench not covered by the first spacer, and a bottom surface of the first trench; a first filling film which fills the first trench, on the first barrier layer; a second barrier layer which extends along a side wall of the second spacer, the portion of the side wall of the second trench not covered by the second spacer, and a bottom surface of the second trench; and a second filling film which fills the second trench on the second barrier layer. I In the first direction, a width of the first trench and a width of the second trench are different from each other, and at a first height from a bottom surface of the substrate, a thickness of the first spacer on the side wall of the first trench is different from a thickness of the second spacer on the side wall of the second trench.

公开(公告)号：US20220392800A1

公开(公告)日：2022-12-08

申请号：US17739114

申请日：2022-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyuk LIM ,  Jong Min BAEK ,  Deok Young JUNG ,  Sung Jin KANG ,  Jang Ho LEE

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/8234

Abstract: There is provided a semiconductor device including an etching stop film which is placed disposed on a substrate; an interlayer insulating film which is disposed on the etching stop film; a trench which penetrates the interlayer insulating film and the etching stop film; a spacer which extends along side walls of the trench; a barrier film which extends along the spacer and a bottom surface of the trench; and a filling film which fills the trench on the barrier film. The trench includes a first trench and a second trench which are spaced apart from each other in a first direction and have different widths from each other in the first direction. A bottom surface of the second trench is placed disposed below a bottom surface of the first trench.

公开(公告)号：US20200219808A1

公开(公告)日：2020-07-09

申请号：US16441042

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soon Gyu HWANG ,  Kyoung Woo LEE ,  YoungWoo CHO ,  IL SUP KIM ,  Su Hyun BARK ,  Young-Ju PARK ,  Jong Min BAEK ,  Min HUH

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first lower wiring line on the substrate, a first insulation layer on the first lower wiring line, a first dielectric barrier layer and a first etch stop layer sequentially stacked on the first insulation layer, a second insulation layer on the first etch stop layer, a first upper wiring line extending through the second insulation layer, the first etch stop layer, and the first dielectric barrier layer, and a first conductive via in the first insulation layer and electrically connecting the first lower wiring line and the first upper wiring line. An upper surface of the first conductive via protrudes above a lower surface of the first upper wiring line.

公开(公告)号：US20200051909A1

公开(公告)日：2020-02-13

申请号：US16285583

申请日：2019-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Young KIM ,  Kyu Hee HAN ,  Sung Bin PARK ,  Yeong Gil KIM ,  Jong Min BAEK ,  Kyoung Woo LEE ,  Deok Young JUNG

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768

Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.

公开(公告)号：US20250118670A1

公开(公告)日：2025-04-10

申请号：US18634162

申请日：2024-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Sung KIM ,  Kyeong Beom PARK ,  Su Hyun BARK ,  Jong Min BAEK ,  Jun Hyuk LIM

IPC: H01L23/528 ,  H01L23/522

Abstract: Provided is a semiconductor device and method of manufacturing same, the semiconductor device including: a substrate; an interlayer insulating layer on the substrate; an upper wiring trench in the interlayer insulating layer; an upper wiring layer including an upper wiring barrier layer along a sidewall of the upper wiring trench and a bottom surface of the upper wiring trench, and an upper wiring filling layer on the upper wiring barrier layer, wherein the upper wiring filling layer fills an inside of the upper wiring trench; and a first etching stop layer on each of an upper surface of the interlayer insulating layer and an upper surface of the upper wiring layer, the first etching stop layer including: a first portion in contact with an upper surface of the upper wiring filling layer; a second portion in contact with an upper surface of the upper wiring barrier layer; and a third portion in contact with the upper surface of the interlayer insulating layer, wherein a percentage of nitrogen (N) in the first portion is greater than a percentage of nitrogen (N) in the second portion.

公开(公告)号：US20240128332A1

公开(公告)日：2024-04-18

申请号：US18350614

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Shin JANG ,  Jong Min BAEK ,  Sun Ki MIN ,  Na rae OH

IPC: H01L29/417 ,  H01L23/48 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41725 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device comprising: a lower insulating layer; a field insulating layer on the lower insulating layer; an upper insulating layer on the field insulating layer; a first through via in the upper insulating layer; a second through via in the field insulating layer; and a third through via in the lower insulating layer, wherein the second through via is connected to the first and third through vias, and wherein a width of a top surface of the second through via is greater than a width of a bottom surface of the first through via, a width of a bottom surface of the second through via is greater than a width of a top surface of the third through via, and a width of a middle portion of the second through via is greater than the widths of the top surface and the bottom surface of the second through via.

公开(公告)号：US20230126012A1

公开(公告)日：2023-04-27

申请号：US17866904

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-Kil JUNG ,  Sang-Wan NAM ,  Jong Min BAEK ,  Min Ki JEON ,  Woo Chul JUNG ,  Yoon-Hee CHOI

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.

公开(公告)号：US20220285207A1

公开(公告)日：2022-09-08

申请号：US17826366

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Woo Kyung YOU ,  Kyu-Hee HAN ,  Han Seong KIM ,  Jang Ho LEE ,  Sang Shin JANG

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.