公开(公告)号：US20210270899A1

公开(公告)日：2021-09-02

申请号：US17025511

申请日：2020-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyun Choi ,  Hyunchul Hwang ,  Minsu Kim

IPC: G01R31/3185 ,  G06F1/10 ,  G01R31/3177

Abstract: High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.

公开(公告)号：US11063592B2

公开(公告)日：2021-07-13

申请号：US16991659

申请日：2020-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngo Lee ,  Ahreum Kim ,  Minsu Kim

IPC: H03K19/00 ,  H03K3/037 ,  H03K3/33 ,  G06F1/08 ,  H03K17/687

Abstract: An integrated circuit gating circuit includes a first control stage that outputs a first internal signal based on an enable signal and a clock signal, a second control stage that outputs a second internal signal based on the first internal signal and the clock signal, and an output driver that outputs an output clock signal based on the second internal signal. The second control stage includes a first multi-finger transistor that is connected between a second node outputting the second internal signal and the 0-th node and operates based on the clock signal. A first portion of the first multi-finger transistor is formed in a first row defined on a semiconductor substrate, and a second portion of the first multi-finger transistor is formed in a second row defined on the semiconductor substrate.

公开(公告)号：US10884655B2

公开(公告)日：2021-01-05

申请号：US16386645

申请日：2019-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Kim ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Do-Han Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Kwanghee Lee ,  Changmin Lee ,  Insu Choi

IPC: G06F3/06 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/02

Abstract: A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.

公开(公告)号：US20200161339A1

公开(公告)日：2020-05-21

申请号：US16525776

申请日：2019-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyejoo LEE ,  Minsu Kim

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/84

Abstract: A semiconductor device includes a substrate, an insulating layer disposed on the substrate, and a first semiconductor structure and a second semiconductor structure disposed on the insulating layer. Each of the first and second semiconductor structures includes a gate electrode on the insulating layer, a plurality of channel layers that are surrounded by the gate electrode and stacked in a direction perpendicular to a top surface of the insulating layer, and a plurality of dielectric layers disposed between the gate electrode and the channel layers. The amount of the channel layers provided in the first semiconductor structure is greater than the amount of the channel layers provided in the second semiconductor structure.

公开(公告)号：US10038428B2

公开(公告)日：2018-07-31

申请号：US15254272

申请日：2016-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K3/35 ,  H03K3/356 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  H03K19/20 ,  G11C7/10

CPC classification number: H03K3/356121 ,  G11C7/1006 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  H03K19/20

Abstract: In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

公开(公告)号：US09947414B2

公开(公告)日：2018-04-17

申请号：US15377504

申请日：2016-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Song ,  Minsu Kim ,  Il Han Park ,  Su Chang Jeon

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C2207/005

Abstract: An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.

公开(公告)号：US09762214B2

公开(公告)日：2017-09-12

申请号：US14754926

申请日：2015-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim

IPC: H03K3/356

CPC classification number: H03K3/356 ,  H03K3/356173

Abstract: A flip-flop circuit includes an evaluation part connected to a first node and a second node to discharge the second node according to a voltage level of the first node, a conditional delay part connected to the second node to discharge a third node to have a voltage level different from a voltage level of the second node, and a keeper logic part connected to the second node and third node to maintain a voltage level of one of the second and third nodes being not discharged.

公开(公告)号：US12228984B2

公开(公告)日：2025-02-18

申请号：US17861400

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heetae Kim ,  Minsu Kim ,  Jungtae Kim ,  Sanghyun Ryu ,  Dongyoung Lee

IPC: G06F1/32 ,  G01R31/382 ,  G06F1/26

Abstract: An electronic device according to an embodiment may include: a battery; a connector including multiple pins; and at least one processor, and wherein the at least one processor is configured to: identify an external electronic device electrically connected through the connector, identify, among at least two supportable current values, a current value of power to be supplied to the external electronic device, and supply power of the battery to the external electronic device through the connector based on the identified current value.

公开(公告)号：US12149249B2

公开(公告)日：2024-11-19

申请号：US18352171

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ahreum Kim ,  Youngo Lee ,  Minsu Kim ,  Eunhee Choi

IPC: H03K3/00 ,  G06F30/392 ,  H03K3/0233 ,  H03K3/037 ,  H03K17/687 ,  H03K19/094 ,  H03K19/20

Abstract: A flip-flop includes a first master latch in a first row, a second master latch in a second row, a first slave latch in the first row, and a second slave latch in the second row. The first master latch and the second master latch are adjacently disposed in the second direction, and the first slave latch and the second slave latch are adjacently disposed in the second direction.

公开(公告)号：US12126343B2

公开(公告)日：2024-10-22

申请号：US17983929

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwoo Kim ,  Minsu Kim ,  Yonggeol Kim ,  Hyun Lee ,  Hyunchul Hwang

IPC: H03K3/037 ,  H03K3/356 ,  H03K3/3562 ,  H03K19/00

CPC classification number: H03K3/0372 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/3562 ,  H03K19/0002

Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.