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公开(公告)号：US08982618B2
公开(公告)日：2015-03-17
申请号：US13795750
申请日：2013-03-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Hyun Joo , Il-Han Park , Ki-Whan Song
CPC classification number: G11C16/3418 , G11C11/5628 , G11C16/06 , G11C16/10 , G11C16/26
Abstract: A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches.
Abstract translation: 非易失性存储器件包括非易失性存储器芯片，其包括静态锁存器，通过浮动节点接收存储在静态锁存器中的数据的第一和第二动态锁存器以及被配置为存储多位数据的存储器单元。 非易失性存储器件对第一动态锁存器执行刷新操作，其中外部提供的第一单位数据被存储在第一动态锁存器中，对外部提供的第二单位数据存储在第二动态锁存器中的第二动态锁存器执行刷新操作 在第一和第二单个位数据存储在相应的第一和第二动态锁存器中之后，使用存储在第一和第二动态锁存器中的数据对存储器单元进行锁存和编程。
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公开(公告)号：US12020759B2
公开(公告)日：2024-06-25
申请号：US17878019
申请日：2022-07-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jun-Ho Seo , Juwon Lee , Suk-Eun Kang , Dogyeong Lee , Youngwook Jeong , Sang-Hyun Joo
CPC classification number: G11C16/3459 , G06N3/08 , G11C11/5628 , G11C11/5635 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/3495
Abstract: An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.
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公开(公告)号：US11462271B2
公开(公告)日：2022-10-04
申请号：US17126933
申请日：2020-12-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Hak Yun , Jae Woo Im , Sang-Hyun Joo
Abstract: A nonvolatile memory device and an operating method are provided. The nonvolatile memory device includes a memory cell array including a plurality of planes, each plane including a plurality of memory blocks, an address decoder connected to the memory cell array, a voltage generator configured to apply an operating voltage to the address decoder, a page buffer circuit including page buffers corresponding to each of the planes, a data input/output circuit connected to the page buffer circuit configured to input and output data and a control unit configured to control the operation of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit, wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block.
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公开(公告)号：US10067825B2
公开(公告)日：2018-09-04
申请号：US15061349
申请日：2016-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Woo Im , Sang-Hyun Joo
Abstract: A memory cell array includes memory cells that are formed in vertical channels extended in a vertical direction with respect to a substrate. The vertical channels are arranged in a zig-zag manner in parallel to the first direction. A read-write circuit is connected to the memory cells via bit lines. An address decoder decodes an address to provide decoded address signals to the read-write circuit. The memory cells include outer cells and inner cells. A distance between one of the outer cells and a common source node is smaller than a distance between one of the inner cells and the common source node. Data of the memory cells are distributed among ECC sectors and a data input-output order of the memory cells is arranged such that each ECC sector has substantially the same number of the outer cells and the inner cells. Each ECC sector corresponds to an ECC operation unit.
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公开(公告)号：US09959933B2
公开(公告)日：2018-05-01
申请号：US15670290
申请日：2017-08-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ho-Jun Lee , Sang-Hyun Joo
CPC classification number: G11C16/3495 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/26 , G11C29/50004 , G11C2029/0409 , G11C2029/1202 , G11C2029/1204
Abstract: A method of operating a non-volatile memory device includes selecting a first select transistor from among a plurality of select transistors included in a NAND string, and performing a check operation on a first threshold voltage of the first select transistor. The check operation includes comparing the first threshold voltage with a first lower-limit reference voltage level, and performing a program operation on the first select transistor when the first threshold voltage is lower than the first lower-limit reference voltage level. When the first threshold voltage is equal to or higher than the first lower-limit reference voltage level, the check operation on the first threshold voltage is ended.
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Patent Agency Ranking
16.发明授权Method of programming non-volatile memory device and apparatuses for performing the method 有权用于执行该方法的非易失性存储器件和装置的编程方法公开(公告)号：US08953385B2
公开(公告)日：2015-02-10
申请号：US14071020
申请日：2013-11-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Hyun Joo
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/30 , G11C16/3404 , G11C16/3454 , G11C16/3459
Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation.
Abstract translation: 提供了一种非易失性存储器件。 非易失性存储器件包括包括多个非易失性存储器单元的单元串; 以及操作控制块，其被配置为在编程操作期间向连接到所述多个非易失性存储单元中的所选择的非易失性存储单元的字线提供编程电压，用于在编程期间向所述字线提供第一负电压 取样操作，并且被配置为在程序验证操作期间将第二负电压作为验证电压提供给字线。
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17.发明申请PAGE BUFFER, MEMORY DEVICE COMPRISING PAGE BUFFER, AND RELATED METHOD OF OPERATION 有权页面缓冲器，包含页面缓冲器的存储器件以及相关的操作方法公开(公告)号：US20130250678A1
公开(公告)日：2013-09-26
申请号：US13718105
申请日：2012-12-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Hyun Joo , Il-Han Park , Ki-Hwan Song
CPC classification number: G11C11/24 , G11C16/02 , G11C16/10 , G11C2216/14
Abstract: A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node.
Abstract translation: 页面缓冲器包括被配置为存储从外部设备接收的数据的静态锁存器和配置成通过浮动节点接收存储在静态锁存器中的数据的动态锁存器，该动态锁存器包括存储电容器，写入晶体管被配置为写入 浮动节点到存储电容器的数据，以及被配置为读取存储电容器的数据的读取晶体管，以及共享浮动节点的写入晶体管和读取晶体管。
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公开(公告)号：US12112056B2
公开(公告)日：2024-10-08
申请号：US18202692
申请日：2023-05-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Hyun Joo
CPC classification number: G06F3/0652 , G06F3/0604 , G06F3/0679 , G11C11/5635 , G11C16/14 , G11C16/16 , G11C2211/5642
Abstract: In some embodiments, a non-volatile memory device includes a control logic circuit configured to generate a program signal and an erase signal based on control signals, a voltage generator configured to generate a program voltage and an erase voltage based on the program signal and the erase signal, a memory cell array including a memory cell, a string select transistor coupled to the memory cell, a bit-line coupled to the string select transistor, and a string select line coupled to the string select transistor, and a page buffer circuit coupled to the bit-line, and including a first precharge transistor that is configured to operate based on the program signal and the erase signal. The first precharge transistor is configured to apply the program voltage and the erase voltage to the bit-line in response to the program signal and the erase signal, respectively.
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公开(公告)号：US20180373592A1
公开(公告)日：2018-12-27
申请号：US16121072
申请日：2018-09-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Woo Im , Sang-Hyun Joo
IPC: G06F11/10
CPC classification number: G06F11/1068 , G11C29/52
Abstract: A memory cell array includes memory cells that are formed in vertical channels extended in a vertical direction with respect to a substrate. The vertical channels are arranged in a zigzag manner in parallel to the first direction. A read-write circuit is connected to the memory cells via bit lines. An address decoder decodes an address to provide decoded address signals to the read-write, circuit. The memory cells include outer cells and inner cells. A distance between one of the outer cells and a common source node is smaller than a distance between one of the inner cells and the common source node. Data of the memory cells are distributed among ECC sectors and a data input-output order of the memory cells is arranged such that each ECC sector has substantially the same number of the outer cells and the inner cells. Each ECC sector corresponds to an ECC operation unit.
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公开(公告)号：US09892795B2
公开(公告)日：2018-02-13
申请号：US15350134
申请日：2016-11-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Hyun Joo , KeeHo Jung
CPC classification number: G11C16/26 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/16 , G11C16/3445
Abstract: A nonvolatile memory device includes a memory cell array, a row decoder, and page buffer, and control logic. The memory cell array includes cell strings connected to select lines. Each select line is connected to two or more cell strings, each cell string includes memory cells connected to a plurality of word lines, and a select transistor is connected to a corresponding one of the select lines. The row decoder sequentially selects the select lines in a read operation. A page buffer obtains a read result of the two or more cell strings when a corresponding select line is selected and accumulates read results of the cell strings when the select lines are sequentially selected. The control logic controls a subsequent operation based on the accumulated read results.
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