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11.发明申请公开(公告)号：US20190279720A1
公开(公告)日：2019-09-12
申请号：US16205334
申请日：2018-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Wan NAM , Dong-Hun KWAK , Chi-Weon YOON
IPC: G11C16/16 , G11C16/04 , H01L27/11582 , H01L27/11573
Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.
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12.发明申请公开(公告)号：US20180046574A1
公开(公告)日：2018-02-15
申请号：US15790583
申请日：2017-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chi Weon YOON , Dong Hyuk CHAE , Sang-Wan NAM , Jung-Yun YUN
CPC classification number: G06F12/0646 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F2212/2022 , G11C5/025 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C2211/5648
Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
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公开(公告)号：US20160284412A1
公开(公告)日：2016-09-29
申请号：US15174183
申请日：2016-06-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Wan NAM , Kuihan KO , Yang-Lo AHN , Kitae PARK
CPC classification number: G11C16/10 , G11C7/04 , G11C16/0483 , G11C16/08 , G11C16/3427
Abstract: A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.
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14.发明申请NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE DEVICE, AND MEMORY SYSTEM 有权非易失性存储器件和用于编程器件和存储器系统的方法公开(公告)号：US20130279260A1
公开(公告)日：2013-10-24
申请号：US13919127
申请日：2013-06-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chi-Weon YOON , Dong-Hyuk CHAE , Sang-Wan NAM , Sung-Won Yun
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/3418
Abstract: A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.
Abstract translation: 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。
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15.发明申请公开(公告)号：US20210117321A1
公开(公告)日：2021-04-22
申请号：US17137942
申请日：2020-12-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chi Weon YOON , Dong Hyuk CHAE , Sang-Wan NAM , Jung-Yun YUN
Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20200135758A1
公开(公告)日：2020-04-30
申请号：US16440299
申请日：2019-06-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won PARK , Sang-Wan NAM , Bong-Soon LIM
IPC: H01L27/11582 , G11C16/04 , G11C16/14 , G11C16/10 , G11C16/26 , H01L27/1157 , H01L27/11573 , G06F3/06
Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.
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公开(公告)号：US20190035466A1
公开(公告)日：2019-01-31
申请号：US16035958
申请日：2018-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wan-Dong KIM , Tae-Hyun KIM , Sang-Wan NAM , Sang-Soo PARK , Jae-Yong JEONG
Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.
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公开(公告)号：US20160379716A1
公开(公告)日：2016-12-29
申请号：US15259765
申请日：2016-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan NAM , Kang-Bin LEE , Junghoon PARK
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3459 , H01L27/1157 , H01L27/11582
Abstract: An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.
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公开(公告)号：US20160055914A1
公开(公告)日：2016-02-25
申请号：US14931936
申请日：2015-11-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Wan NAM , Kuihan KO , Yang-Lo AHN , Kitae PARK
CPC classification number: G11C16/10 , G11C7/04 , G11C16/0483 , G11C16/08 , G11C16/3427
Abstract: A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.
Abstract translation: 非易失性存储器件的驱动方法包括接收程序命令和地址。 该方法包括根据与所接收的地址相对应的所选择的字线的位置来改变由未选字线形成的多个区域中的多个相邻区域的数量。 该方法还包括将不同的区域电压施加到相邻区域和剩余区域的数量。 非易失性存储装置包括形成为穿过板状堆叠在基板上的字线的多个串。
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公开(公告)号：US20140293693A1
公开(公告)日：2014-10-02
申请号：US14197723
申请日：2014-03-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Wan NAM , Kuihan KO , Yang-Lo AHN , Kitae PARK
CPC classification number: G11C16/10 , G11C7/04 , G11C16/0483 , G11C16/08 , G11C16/3427
Abstract: A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape.
Abstract translation: 非易失性存储器件的驱动方法包括接收程序命令和地址。 该方法包括根据与所接收的地址相对应的所选择的字线的位置来改变由未选字线形成的多个区域中的多个相邻区域的数量。 该方法还包括将不同的区域电压施加到相邻区域和剩余区域的数量。 非易失性存储装置包括形成为穿过板状堆叠在基板上的字线的多个串。
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