公开(公告)号：US10892278B2

公开(公告)日：2021-01-12

申请号：US16509169

申请日：2019-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  Hongsuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11582 ,  H01L29/06 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11565 ,  H01L29/10 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

公开(公告)号：US10651191B2

公开(公告)日：2020-05-12

申请号：US15864410

申请日：2018-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  HongSuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/423 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/51

Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.

公开(公告)号：US20180097006A1

公开(公告)日：2018-04-05

申请号：US15480983

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11556 ,  H01L29/08 ,  H01L27/11582 ,  H01L29/10

CPC classification number: H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42364

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

公开(公告)号：US20220352203A1

公开(公告)日：2022-11-03

申请号：US17859631

申请日：2022-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Junghwan Kim ,  Chanhyoung Kim

IPC: H01L27/11582 ,  H01L29/10

Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base, layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure arid a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conductive layer has an extension portion extending along a surface of the vertical channel layer in the extended area of the vertical structure.

公开(公告)号：US20210305276A1

公开(公告)日：2021-09-30

申请号：US17076306

申请日：2020-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Seulye Kim ,  Jung-Hwan Kim

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.

公开(公告)号：US10396094B2

公开(公告)日：2019-08-27

申请号：US15849121

申请日：2017-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hoon Choi ,  Sunggil Kim ,  Seulye Kim ,  Hongsuk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.

公开(公告)号：US10263006B2

公开(公告)日：2019-04-16

申请号：US15480983

申请日：2017-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gil Kim ,  Ji-Hoon Choi ,  Dongkyum Kim ,  Jintae Noh ,  Seulye Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jaeyoung Ahn

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/423

Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

公开(公告)号：US11910607B2

公开(公告)日：2024-02-20

申请号：US17881707

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H10B43/27 ,  H01L29/04 ,  H01L29/792 ,  H01L29/423 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L29/04 ,  H01L29/42344 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US11737277B2

公开(公告)日：2023-08-22

申请号：US17523014

申请日：2021-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon Choi ,  Sung Gil Kim ,  Seulye Kim ,  Jung Ho Kim ,  Hong Suk Kim ,  Phil Ouk Nam ,  Jae Young Ahn ,  Han Jin Lim

IPC: H10B43/27 ,  H10B43/10 ,  H01L23/528

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B43/10

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

公开(公告)号：US11626414B2

公开(公告)日：2023-04-11

申请号：US16903026

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim

IPC: H01L27/11568 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/11582 ,  G11C5/02

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.