公开(公告)号：US20210042046A1

公开(公告)日：2021-02-11

申请号：US17082448

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US10884655B2

公开(公告)日：2021-01-05

申请号：US16386645

申请日：2019-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Kim ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Do-Han Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Kwanghee Lee ,  Changmin Lee ,  Insu Choi

IPC: G06F3/06 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/02

Abstract: A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.

公开(公告)号：US10740010B2

公开(公告)日：2020-08-11

申请号：US16205357

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Joon Kim ,  Dae-Jeong Kim ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F3/06

Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.

公开(公告)号：US12132501B2

公开(公告)日：2024-10-29

申请号：US17895227

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Sung-Joon Kim ,  Heedong Kim ,  Minsu Bae ,  Ilwoong Seo ,  Mijin Lee ,  Seung Ju Lee ,  Hyan Suk Lee ,  Insu Choi ,  Kideok Han

IPC: H03M13/19 ,  G06F11/10 ,  G11C5/04 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/00

CPC classification number: H03M13/19 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1048 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/611 ,  G11C5/04

Abstract: A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

公开(公告)号：US11656929B2

公开(公告)日：2023-05-23

申请号：US17345276

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mi Jin Lee ,  Dong-Yoon Kim ,  Min-Hyouk Kim ,  Sung-Joon Kim ,  Sung Up Moon ,  Jong Young Lee

IPC: G06F11/07

CPC classification number: G06F11/0778 ,  G06F11/073 ,  G06F11/0772 ,  G06F11/0784 ,  G06F11/0787 ,  G06F11/0793

Abstract: A memory module includes; dynamic random access memories (DRAMs), a controller configured to control operation of the DRAMs, and an active device configured, in response to detection of an error occurring in at least one of the DRAMs, to generate an interrupt and store error information corresponding to the error.

公开(公告)号：US11586848B2

公开(公告)日：2023-02-21

申请号：US16268762

申请日：2019-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Jin Yun ,  Sung-Joon Kim ,  Sang-Hoan Chang

IPC: G06K9/62 ,  G06K9/00 ,  G06V20/00

Abstract: An object recognition device including an artificial neural network (NN) engine configured to receive learning data and weights, make an object recognition model (ORM) learn by using the received information, and provide selected weight data including weights from the selected portion of the weights, and further configured to receive a feature vector, and apply the feature vector extracted from an object data that constructs the object and the selected weight data to the learned ORM to provide an object recognition result, a nonvolatile memory (NVM) configured to store the learned ORM, and an error correction code (ECC) engine configured to perform an ECC encoding on the selected weight data to generate parity data, provide the selected weight data and the parity data to the NVM, and provide the selected weight data to the NN engine by performing an ECC decoding on the selected weight data based on the parity data.

公开(公告)号：US11157342B2

公开(公告)日：2021-10-26

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Yongjun Yu ,  Insu Choi ,  Hui-Chung Byun ,  JongYoung Lee

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US20190050352A1

公开(公告)日：2019-02-14

申请号：US16165139

申请日：2018-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changho Yun ,  Sung-Joon Kim

IPC: G06F13/16 ,  G11C11/406

CPC classification number: G06F13/1689 ,  G11C5/04 ,  G11C7/1084 ,  G11C11/406 ,  G11C29/00 ,  G11C2207/2254

Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.

公开(公告)号：US20180151218A1

公开(公告)日：2018-05-31

申请号：US15691828

申请日：2017-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANG-HO YUN ,  Min-Su Kim ,  Sung-Joon Kim ,  So-Ra Park ,  Hyun-Jung Yoo

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G11C11/40611 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40618

Abstract: A method of operating a memory device, a first setting signal is received by a first memory device among a plurality of memory devices. The first memory device has a first storage capacity, and the memory devices may be connected to one another by a single channel. A second setting signal is received by a second memory device among the plurality of memory devices. The second memory device has a second storage capacity different from the first storage capacity. N refresh operations are performed by the first memory device based on a first refresh command and the first setting signal during a first refresh period. M refresh operations are performed by the second memory device based on a second refresh command and the second setting signal during a second refresh period. A duration of the second refresh period is substantially the same as a duration of the first refresh period.

公开(公告)号：US20240202069A1

公开(公告)日：2024-06-20

申请号：US18376637

申请日：2023-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Jin PARK ,  Sung-Joon Kim ,  Ho-Young Lee ,  Kyung-Hee Han

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/106 ,  G06F11/076 ,  G06F11/1068

Abstract: A memory system, a memory controller are provided. The memory system includes: a memory device; and a memory controller configured to: control a patrol scrubbing operation in which data is read from and re-written to the memory device, based on a scrubbing cycle; and adaptively adjust the scrubbing cycle based on a comparison of an error count value of the memory device and a plurality of risk threshold values.