公开(公告)号：US09929174B1

公开(公告)日：2018-03-27

申请号：US15337235

申请日：2016-10-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yuki Mizutani ,  Hiroyuki Ogawa ,  Fumiaki Toyama ,  Masaaki Higashitani ,  Fumitaka Amano ,  Kota Funayama ,  Akihiro Ueda

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/786 ,  H01L29/792 ,  H01L27/11568 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/0692 ,  H01L29/78642 ,  H01L29/7926

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures including a memory film and a vertical semiconductor channel are formed through the alternating stack in an array configuration. Backside trenches extending along a lengthwise direction are formed through the alternating stack. Backside recesses are formed by removing the sacrificial material layers. Filling of the backside recesses with electrically conductive layers can be performed without voids or with minimal voids by arranging the memory stack structures with a non-uniform pitch. The non-uniform pitch may be along the direction perpendicular to the lengthwise direction such that the nearest neighbor distance among the memory stack structures is at a minimum between the backside trenches. Alternatively or additionally, the pitch may be modulated along the lengthwise direction to provide wider spacing regions that extend perpendicular to the lengthwise direction.

公开(公告)号：US09780034B1

公开(公告)日：2017-10-03

申请号：US15183195

申请日：2016-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Kota Funayama ,  Ryoichi Ehara ,  Youko Furihata ,  Zhenyu Lu ,  Tong Zhang ,  Tadashi Nakamura

IPC: H01L29/792 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a monolithic three-dimensional memory device includes forming a first alternating stack over a substrate, forming an insulating cap layer, forming a first memory opening through the insulating cap layer and the first alternating stack, forming a sacrificial pillar structure in the first memory opening, forming a second alternating stack, forming a second memory opening, forming an inter-stack memory opening, forming a memory film and a first semiconductor channel layer in the inter-stack memory opening, anisotropically etching a horizontal bottom portion of the memory film and the first semiconductor channel layer to expose the substrate at the bottom of the inter-stack memory opening such that damage to portions of the first semiconductor channel layer and the memory film located adjacent to the insulating cap layer is reduced or avoided, and forming a second semiconductor channel layer in contact with the exposed substrate in the inter-stack memory opening.

公开(公告)号：US09754963B1

公开(公告)日：2017-09-05

申请号：US15243260

申请日：2016-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takeshi Kawamura ,  Kota Funayama

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/105

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support pillar structures are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed over the first tier structure. Memory stack structures and second support pillar structures are formed through the second tier structure. The first and second sacrificial material layers are replaced with first and second electrically conductive layers while the first support pillar structures, the second support pillar structures, and the memory stack structures provide structural support to the first and second insulating layers. By limiting the spatial extent of the first support pillar structures within the first tier structure, electrical short to backside contact via structures can be reduced.

公开(公告)号：US09613971B2

公开(公告)日：2017-04-04

申请号：US14808475

申请日：2015-07-24

Applicant: SanDisk Technologies LLC

Inventor： Masahiro Yaegashi ,  Kota Funayama ,  Takeshi Kawamura ,  Dai Iwata

IPC: H01L27/11 ,  H01L27/11524 ,  H01L29/49 ,  H01L29/40 ,  H01L21/265 ,  H01L21/28 ,  H01L29/788 ,  H01L29/167 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L27/11524 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/768 ,  H01L23/528 ,  H01L29/167 ,  H01L29/401 ,  H01L29/495 ,  H01L29/7883

Abstract: A NAND flash memory array includes a select line having a first edge region containing a first portion of floating gate material and a second edge region containing a second portion of floating gate material, and having a central region between the first edge region and the second edge region where no floating gate material is present.

公开(公告)号：US12133388B2

公开(公告)日：2024-10-29

申请号：US17583456

申请日：2022-01-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kota Funayama ,  Satoshi Shimizu ,  Koichi Matsuno

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A memory device includes a lower source-level semiconductor layer, a source contact layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and electrically conductive layers, and a memory opening fill structure vertically extending through the alternating stack and down to an upper portion of the lower source-level semiconductor layer. The memory opening fill structure includes a vertical semiconductor channel, a memory film laterally surrounding the vertical semiconductor channel, and an annular semiconductor cap contacting a bottom surface of the memory film and contacting a top surface segment of the source contact layer. The annular semiconductor cap may be employed as an etch stop structure during a manufacturing process.

公开(公告)号：US10658377B2

公开(公告)日：2020-05-19

申请号：US16019677

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tomohiro Kubo ,  Koji Miyata ,  Kota Funayama

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/11573

Abstract: A first memory film and a sacrificial fill structure are formed within each first-tier memory opening through a first alternating stack of first insulating layers and first spacer material layers. A second alternating stack of second insulating layers and second spacer material layers is formed over the first alternating stack, and a second-tier memory opening is formed over each sacrificial fill structure. A second memory film is formed in each upper opening, and the sacrificial fill structures are removed from underneath the second-tier memory openings to form memory openings. A semiconductor channel is formed on each vertically neighboring pair of a first memory film and a second memory film as a continuous layer. The first memory film is protected by the sacrificial fill structure during formation of the second-tier memory openings.

公开(公告)号：US09978766B1

公开(公告)日：2018-05-22

申请号：US15347101

申请日：2016-11-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro Hosoda ,  Takeshi Kawamura ,  Yoko Furihata ,  Kota Funayama

IPC: H01L29/76 ,  H01L27/11556 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings are formed through the first tier structure. A dielectric material portion providing electrical isolation from the substrate is formed in each first memory openings. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed the first tier structure. Second support openings and second memory openings are formed through the second tier structure above the first support openings and the first memory openings. Memory stack structures are formed in inter-tier openings formed by adjoining the first and second memory openings. The dielectric material portions provide electrical isolation between the substrate and the vertical semiconductor layers formed within support pillar structures to prevent or reduce electrical shorts to the substrate through the support pillar structures.

公开(公告)号：US09859363B2

公开(公告)日：2018-01-02

申请号：US15155639

申请日：2016-05-16

Applicant: SANDISK TECHNOLOGIES, LLC.

Inventor： Zhenyu Lu ,  Kota Funayama ,  Chun-Ming Wang ,  Jixin Yu ,  Chenche Huang ,  Tong Zhang ,  Daxin Mao ,  Johann Alsmeier ,  Makoto Yoshida ,  Lauren Matsumoto

IPC: H01L29/06 ,  H01L21/76 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/24 ,  H01L27/112

CPC classification number: H01L29/0649 ,  H01L27/1128 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481

Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.