公开(公告)号：US20240258317A1

公开(公告)日：2024-08-01

申请号：US18631240

申请日：2024-04-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyokazu SHISHIDO ,  Hiroshi NAKATSUJI ,  Dai IWATA ,  Koichi MATSUNO

IPC: H01L27/092 ,  H01L21/762 ,  H01L27/02 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/76224 ,  H01L27/0207 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6656 ,  H01L27/0629

Abstract: A first field effect transistor includes a first active region and a first gate electrode that includes a first semiconductor gate electrode portion and a first metallic gate electrode portion. The first active region includes a first source region and a first drain region that are laterally spaced from each other by a first channel along a first channel direction. The first gate electrode laterally extends along a first gate electrode direction that is perpendicular to the first channel direction. A maximum lateral extent of the first metallic gate electrode portion along the first gate electrode direction is greater than a maximum lateral extent of the first semiconductor gate electrode portion along the first gate electrode direction.

公开(公告)号：US20240237354A1

公开(公告)日：2024-07-11

申请号：US18613763

申请日：2024-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kartik SONDHI ,  Senaka KANAKAMEDALA ,  Koichi MATSUNO

IPC: H10B43/27 ,  H01L23/522 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B43/10

Abstract: A three-dimensional memory device includes: an alternating stack of insulating layers and electrically conductive layers having stepped surfaces in a contact region; memory openings vertically extending through the alternating stack; memory opening fill structures located in the memory openings; a retro-stepped dielectric material portion overlying the stepped surfaces; and a layer contact assembly vertically extending through the retro-stepped dielectric material portion and through a subset of layers in the alternating stack and including: a dielectric pillar structure that is laterally surrounded by the subset of layers in the alternating stack; and a layer contact via structure including a cylindrical conductive material portion that vertically extends through the retro-stepped dielectric material portion and a downward-protruding tubular portion adjoined to a bottom end of the cylindrical conductive portion and having an annular bottom surface that contacts an electrically conductive layer within the subset of layers in the alternating stack.

公开(公告)号：US20240179906A1

公开(公告)日：2024-05-30

申请号：US18352752

申请日：2023-07-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Naohiro HOSODA ,  Kazuki ISOZUMI ,  Takayuki MAEKURA ,  Hiroyuki OGAWA ,  Koichi MATSUNO

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory cells. An integrated line-and-via structure is provided, which is a unitary structure including a metallic plate portion that is a portion of or laterally contacts an electrically conductive layer, and a metallic via portion that vertically extends through dielectric material plates that overlie the metallic plate portion.

公开(公告)号：US20220254728A1

公开(公告)日：2022-08-11

申请号：US17510807

申请日：2021-10-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  Johann ALSMEIER

IPC: H01L23/544 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack, and a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack. At least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region.

公开(公告)号：US20240395710A1

公开(公告)日：2024-11-28

申请号：US18798250

申请日：2024-08-08

Applicant: Sandisk Technologies LLC

Inventor： Koichi MATSUNO ,  Tomohiro KUBO ,  Johann ALSMEIER

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor structure includes alternating stacks of insulating layers and electrically conductive layers which are located over a substrate and are laterally spaced apart among one another by first backside trenches and second backside trenches that are interlaced along a horizontal direction, first backside trench fill structures located in the first backside trenches, and second backside trench fill structures located in the second backside trenches. Each of the first backside trench fill structures includes a respective set of first backside bridge support structures comprising a first material, and each of the second backside trench fill structures includes a respective set of second backside bridge support structures comprising a second material that is different from the first material.

公开(公告)号：US20240274191A1

公开(公告)日：2024-08-15

申请号：US18356825

申请日：2023-07-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  Johann ALSMEIER

IPC: G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes a first-tier alternating stack of first insulating layers and electrically conductive layers located over a substrate, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack, a memory stack structure vertically extending through the first-tier alternating stack and the second-tier alternating stack, and a first support and contact assembly vertically extending through the first-tier alternating stack and the second-tier alternating stack. The first support and contact assembly includes a first contact via structure contacting an annular top surface of an electrically conductive layer, a first dielectric pillar structure underlying the reference-level electrically conductive layer, and a first-tier dielectric spacer that laterally surrounds the first contact via structure.

公开(公告)号：US20240268115A1

公开(公告)日：2024-08-08

申请号：US18357702

申请日：2023-07-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Wei CAO ,  Xiang YANG ,  Koichi MATSUNO

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B43/35 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel including a first semiconductor material, and source structure including an interfacial source layer and a primary source layer. The interfacial source layer includes a second semiconductor material that has a different band gap from a band gap of the first semiconductor material and is in contact with an end portion of the vertical semiconductor channel. The primary source layer includes a third semiconductor material that has a different band gap from the band gap of the second semiconductor material, and the primary source layer is in contact with the interfacial source layer.

公开(公告)号：US20230411306A1

公开(公告)日：2023-12-21

申请号：US17807266

申请日：2022-06-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L23/562 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric moat fill structure that includes a nested structure including, from outside to inside, an outer dielectric liner having a first Young's modulus, an outer material layer having a second Young's modulus greater than the first Young's modulus, a dielectric fill material portion, an inner material layer having the second Young's modulus, and an inner dielectric liner having the first Young's modulus, a vertically alternating sequence of insulating plates and dielectric material plates at least partially laterally surrounded by the dielectric moat fill structure, and an interconnection via structure vertically extending the vertically alternating sequence.

公开(公告)号：US20230246084A1

公开(公告)日：2023-08-03

申请号：US17587470

申请日：2022-01-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Koichi MATSUNO

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11582

CPC classification number: H01L29/4234 ,  H01L29/40117 ,  H01L27/11582

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

公开(公告)号：US20230240070A1

公开(公告)日：2023-07-27

申请号：US17583456

申请日：2022-01-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kota FUNAYAMA ,  Satoshi SHIMIZU ,  Koichi MATSUNO

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A memory device includes a lower source-level semiconductor layer, a source contact layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and electrically conductive layers, and a memory opening fill structure vertically extending through the alternating stack and down to an upper portion of the lower source-level semiconductor layer. The memory opening fill structure includes a vertical semiconductor channel, a memory film laterally surrounding the vertical semiconductor channel, and an annular semiconductor cap contacting a bottom surface of the memory film and contacting a top surface segment of the source contact layer. The annular semiconductor cap may be employed as an etch stop structure during a manufacturing process.