公开(公告)号：US20220254728A1

公开(公告)日：2022-08-11

申请号：US17510807

申请日：2021-10-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  Johann ALSMEIER

IPC: H01L23/544 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack, and a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack. At least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region.

公开(公告)号：US20210159248A1

公开(公告)日：2021-05-27

申请号：US16694340

申请日：2019-11-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Johann ALSMEIER

IPC: H01L27/11597 ,  G11C11/22 ,  G11C5/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11587 ,  H01L27/1159

Abstract: A ferroelectric field effect transistor (FeFET) includes a semiconductor channel, a source region contacting one end of the semiconductor channel, a drain region contacting a second end of the semiconductor channel, a gate electrode, a ferroelectric gate dielectric layer located between the semiconductor channel and the gate electrode, and a bidirectional selector material layer located between the gate electrode and the ferroelectric gate dielectric layer.

公开(公告)号：US20210050360A1

公开(公告)日：2021-02-18

申请号：US16539124

申请日：2019-08-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann ALSMEIER ,  Murshed CHOWDHURY ,  Raiden MATSUNO

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C5/06

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, gate electrodes vertically extending through each of the source layers and the drain layers of the alternating stack, memory films laterally surrounding a respective one of the gate electrodes, and semiconductor channels laterally surrounding a respective one of the memory films and connected to a respective vertically neighboring pair of a source layer and a drain layer. An array of memory openings can vertically extend through the alternating stack, and each of the gate electrodes can be located within a respective one of the memory openings.

公开(公告)号：US20210028149A1

公开(公告)日：2021-01-28

申请号：US16523029

申请日：2019-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Johann ALSMEIER

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads, providing a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, and bonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads.

公开(公告)号：US20200251149A1

公开(公告)日：2020-08-06

申请号：US16269301

申请日：2019-02-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Zhixin CUI ,  Akio NISHIDA ,  Johann ALSMEIER ,  Yan LI ,  Steven SPROUSE

IPC: G11C5/06 ,  G06F11/08 ,  G11C8/14 ,  H01L25/065 ,  H01L27/105 ,  H01L23/498 ,  H01L23/538

Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.

公开(公告)号：US20200235090A1

公开(公告)日：2020-07-23

申请号：US16251954

申请日：2019-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Murshed CHOWDHURY ,  Kwang-Ho KIM ,  James KAI ,  Johann ALSMEIER

IPC: H01L27/06 ,  H01L27/108 ,  H01L27/11529 ,  H01L27/1157 ,  H01L23/48 ,  H01L23/00 ,  G11C5/02

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.

公开(公告)号：US20190035803A1

公开(公告)日：2019-01-31

申请号：US15784549

申请日：2017-10-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Masanori TSUTSUMI ,  Shinsuke YADA ,  Sayako NAGAMINE ,  Johann ALSMEIER

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529

Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.

公开(公告)号：US20190027488A1

公开(公告)日：2019-01-24

申请号：US15818061

申请日：2017-11-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann ALSMEIER ,  Shinsuke YADA ,  Akihisa SAI ,  Sayako NAGAMINE ,  Takashi ORIMOTO ,  Tong ZHANG

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768

Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.

公开(公告)号：US20180138189A1

公开(公告)日：2018-05-17

申请号：US15354067

申请日：2016-11-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Murshed CHOWDHURY ,  Jin LIU ,  Johann ALSMEIER

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02494 ,  H01L21/02587 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/41741 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/518

Abstract: A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

公开(公告)号：US20240127864A1

公开(公告)日：2024-04-18

申请号：US18350573

申请日：2023-07-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masaaki HIGASHITANI ,  James KAI ,  Johann ALSMEIER

IPC: G11C5/06 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C5/063 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device includes a first memory block containing first word lines and a first source layer segment, and a second memory block containing second word lines and a second source layer segment which is electrically isolated from the first source layer segment. The first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block.