公开(公告)号：US20120032355A1

公开(公告)日：2012-02-09

申请号：US12984542

申请日：2011-01-04

Applicant: Ching-Chiun Wang ,  Kang-Feng Lee ,  Feng-Yu Tsai ,  Ming Hom Zheng ,  Chih-Yung Huang ,  Shih-Chin Lin ,  Jen-Rong Huang

Inventor： Ching-Chiun Wang ,  Kang-Feng Lee ,  Feng-Yu Tsai ,  Ming Hom Zheng ,  Chih-Yung Huang ,  Shih-Chin Lin ,  Jen-Rong Huang

IPC: H01L23/28 ,  H01L21/56 ,  C08F8/42

CPC classification number: C08F8/42 ,  H01L31/0481 ,  H01L33/56 ,  Y02E10/50 ,  C08F216/06

Abstract: Disclosed is an encapsulation film. An inorganic oxide film is formed on an organic sealing layer by an atomic layer deposition (ALD) to form the encapsulation film, wherein the organic sealing layer is a polymer containing hydrophilic groups. The organic sealing layer and the inorganic oxide layer have covalent bondings therebetween. The encapsulation film can solve the moisture absorption problem of conventional organic sealing layers, thereby being suitable for use as a package of optoelectronic devices.

Abstract translation: 公开了一种封装膜。 通过原子层沉积（ALD）在有机密封层上形成无机氧化物膜以形成包封膜，其中有机密封层是含有亲水基团的聚合物。 有机密封层和无机氧化物层之间具有共价键。 该封装膜可以解决传统的有机密封层的吸湿问题，从而适用于光电器件的封装。

公开(公告)号：US20050185448A1

公开(公告)日：2005-08-25

申请号：US10708328

申请日：2004-02-24

Applicant: Shih-Chin Lin

Inventor： Shih-Chin Lin

IPC: G11C11/00 ,  G11C11/412

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) has a plurality of SRAM cells, a first switch unit, a second switch unit, and a capacitor. During read/write operations of the SRAM cells, the first switch unit and the second switch unit are turned on so that two power terminals of the SRAM cells respectively electrically connect to VDD and VSS and that the capacitor electrically connects between VDD and VSS. When the SRAM cells are not accessed, the first switch unit and the second switch unit are turned off and the capacitor keeps a voltage gap between the two power terminals of the SRAM cells greater than a predetermined value.

Abstract translation: 静态随机存取存储器（SRAM）具有多个SRAM单元，第一开关单元，第二开关单元和电容器。 在SRAM单元的读/写操作期间，第一开关单元和第二开关单元导通，使得SRAM单元的两个电源端子分别电连接到V DD和V SS 并且电容器在V DD和V SS之间电连接。 当SRAM单元未被访问时，第一开关单元和第二开关单元断开，并且电容器保持SRAM单元的两个电源端子之间的电压间隙大于预定值。

公开(公告)号：US5995428A

公开(公告)日：1999-11-30

申请号：US32627

申请日：1998-02-27

Applicant: Pien Chien ,  Shih-Chin Lin ,  Charlie Han

Inventor： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

IPC: G01R31/28 ,  G11C29/50 ,  G11C29/00

CPC classification number: G11C29/50 ,  G01R31/2856 ,  G11C11/401

Abstract: A circuit is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this circuit, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

Abstract translation: 提供了一种电路，用于在形成有多个骰子的晶片上使用，每个骰子具有诸如DRAM（动态随机存取存储器）设备的存储器件，以在存储器件上执行老化操作，以便测试 可靠性。 通过该电路，在切割线中用作参考标记的划线中形成多个焊盘。 这些焊盘用于将外部产生的老化使能信号和直流偏置电压传送到每个存储器件。 由于用于老化线的焊盘形成在划线中，所以它们在形成每个存储器件的骰子上不会占用额外的空间。 老化操作更加方便，快捷，性价比高。

公开(公告)号：US08576653B2

公开(公告)日：2013-11-05

申请号：US13175437

申请日：2011-07-01

Applicant: Shih-Chin Lin ,  Pei-Geng Ma ,  Yen-Hsueh Huang

Inventor： Shih-Chin Lin ,  Pei-Geng Ma ,  Yen-Hsueh Huang

IPC: G11C7/00

CPC classification number: G11C11/40615 ,  G11C2211/4013 ,  G11C2211/4061

Abstract: In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation.

Abstract translation: 在伪SRAM的示例性隐藏刷新方法中，接收系统时钟。 系统时钟信号的占空比时段适于执行诸如写入或读取操作之类的数据访问操作。 产生经受系统时钟信号控制的刷新时钟信号。 刷新时钟信号的占空比周期与系统时钟信号的占空比周期不重叠。 然后，刷新控制脉冲由刷新时钟信号的占空比周期的起始边沿触发，以激活字线，以执行刷新操作。

公开(公告)号：US20120126418A1

公开(公告)日：2012-05-24

申请号：US12954397

申请日：2010-11-24

Applicant: Chien-Te Feng ,  Shih-Chin Lin

Inventor： Chien-Te Feng ,  Shih-Chin Lin

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/481 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81418 ,  H01L2224/8142 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/8146 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2224/81473 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/83385 ,  H01L2224/85409 ,  H01L2224/85411 ,  H01L2224/85413 ,  H01L2224/85416 ,  H01L2224/85418 ,  H01L2224/8542 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85457 ,  H01L2224/8546 ,  H01L2224/85463 ,  H01L2224/85464 ,  H01L2224/85469 ,  H01L2224/85473 ,  H01L2224/85476 ,  H01L2224/85478 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit (IC) device includes a polymer substrate having a topside surface and a bottomside surface opposite the topside surface, a plurality of through-holes that extend from the topside surface to the bottomside surface, and a plurality of bottom metal pads on the bottomside surface positioned over the plurality of through-holes. At least one IC die having an active topside including a plurality of bond pads and a second side is affixed to the topside surface. Bonding features are coupled to the plurality of bond pads for coupling respective ones of the plurality of bond pads to the plurality bottom metal pads. The bonding features extend into the through-holes to contact the bottom metal pads.

Abstract translation: 集成电路（IC）装置包括具有顶侧表面和与顶侧表面相对的底部表面的聚合物基板，从顶侧表面延伸到底部表面的多个通孔，以及多个底部金属焊盘 底部表面定位在多个通孔上。 具有包括多个接合焊盘的活动顶面和第二侧的至少一个IC管芯固定到顶侧表面。 接合特征耦合到多个接合焊盘，用于将多个接合焊盘中的相应接合焊盘连接到多个底部金属焊盘。 接合特征延伸到通孔中以接触底部金属焊盘。

公开(公告)号：US06970374B2

公开(公告)日：2005-11-29

申请号：US10708328

申请日：2004-02-24

Applicant: Shih-Chin Lin

Inventor： Shih-Chin Lin

IPC: G11C11/00 ,  G11C11/412

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) has a plurality of SRAM cells, a first switch unit, a second switch unit, and a capacitor. During read/write operations of the SRAM cells, the first switch unit and the second switch unit are turned on so that two power terminals of the SRAM cells respectively electrically connect to VDD and VSS and that the capacitor electrically connects between VDD and VSS. When the SRAM cells are not accessed, the first switch unit and the second switch unit are turned off and the capacitor keeps a voltage gap between the two power terminals of the SRAM cells greater than a predetermined value.

Abstract translation: 静态随机存取存储器（SRAM）具有多个SRAM单元，第一开关单元，第二开关单元和电容器。 在SRAM单元的读/写操作期间，第一开关单元和第二开关单元导通，使得SRAM单元的两个电源端子分别电连接到V DD和V SS 并且电容器在V DD和V SS之间电连接。 当SRAM单元未被访问时，第一开关单元和第二开关单元断开，并且电容器保持SRAM单元的两个电源端子之间的电压间隙大于预定值。