公开(公告)号：US20170033075A1

公开(公告)日：2017-02-02

申请号：US15294508

申请日：2016-10-14

Applicant: Advanced Semiconductor, Inc.

Inventor： Min-Fong SHU ,  Yi-Hsiu TSENG ,  Kuan-Neng CHEN ,  Shu-Chiao KUO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/1182 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13623 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13663 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13676 ,  H01L2224/13678 ,  H01L2224/13687 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81096 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81898 ,  H01L2224/83104 ,  H01L2224/83193 ,  H01L2224/92125 ,  H01L2924/00015 ,  H01L2924/15311 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/8109 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053

Abstract: A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.

Abstract translation: 一种接合结构的制造方法包括：（a）提供基板，其中所述基板包括顶表面和邻近所述基板顶表面设置的至少一个接合焊盘，至少一个接合焊盘，其具有倾斜表面，其具有第一 坡; （b）提供半导体元件，其中所述半导体元件包括至少一个支柱，并且至少一个支柱具有具有第二斜率的侧壁，其中所述第一斜率的绝对值小于所述第二斜率的绝对值; 和（c）将至少一个柱结合到所述至少一个接合焊盘中相应的一个焊盘的倾斜表面的一部分上。

公开(公告)号：US09425066B2

公开(公告)日：2016-08-23

申请号：US13684578

申请日：2012-11-26

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang

IPC: H01L23/48 ,  H01L21/32 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H01L21/32 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81449 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2224/8148 ,  H01L2924/12042 ,  H01L2924/381 ,  H05K1/113 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4682 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/016 ,  H05K2203/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings are respectively filled with the conductive structures. Each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part. Each of the connection parts is connected to the corresponding pad part and the corresponding protruding part. Each of the protruding parts has a curved surface that protrudes from the second surface. A process for fabricating the circuit substrate is also provided.

Abstract translation: 电路基板包括电介质层和多个导电结构。 电介质层具有多个导电开口，第一表面和与第一表面相对的第二表面。 每个导电开口连接第一表面和第二表面。 导电开口分别填充有导电结构。 导电结构中的每一个都是整体形成的，并且包括衬垫部分，连接部分和突出部分。 每个连接部分连接到对应的垫部分和相应的突出部分。 每个突出部分具有从第二表面突出的弯曲表面。 还提供了一种用于制造电路基板的工艺。

公开(公告)号：US20140124799A1

公开(公告)日：2014-05-08

申请号：US13830148

申请日：2013-03-14

Applicant: Electronics and Telecommunications Research Institute

Inventor： Doo Hyeb YOUN ,  Choon Gi CHOI ,  Kwang Hyo CHUNG

IPC: H01L33/48 ,  H01L33/08

CPC classification number: H01L33/48 ,  H01L23/373 ,  H01L24/81 ,  H01L24/83 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/08 ,  H01L33/20 ,  H01L33/40 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/06102 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/29023 ,  H01L2224/29034 ,  H01L2224/29193 ,  H01L2224/32238 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/8142 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83409 ,  H01L2224/83411 ,  H01L2224/83418 ,  H01L2224/8342 ,  H01L2224/83447 ,  H01L2224/9211 ,  H01L2924/12041 ,  H01L2933/0016 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01031 ,  H01L2924/014

Abstract: Provided is a light emitting diode, including a sub-mount structure including a first substrate and electrode portions provided on the first substrate, and a light emitting structure mounted on the sub-mount structure to include a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer. The electrode portions may include a first electrode portion and a second electrode portion connected to the first and second semiconductor layers, respectively, and each of the first and second electrode portions may include a first metal layer, a graphene layer, and a second metal layer sequentially provided on the first substrate.

Abstract translation: 本发明提供一种发光二极管，其包括具有第一基板和设置在第一基板上的电极部分的子安装结构，以及安装在子安装结构上的发光结构，包括第一半导体层，第二半导体层， 以及在第一半导体层和第二半导体层之间的有源层。 电极部分可以包括分别连接到第一和第二半导体层的第一电极部分和第二电极部分，并且第一和第二电极部分中的每一个可以包括第一金属层，石墨烯层和第二金属层 依次设置在第一基板上。

公开(公告)号：US20140077357A1

公开(公告)日：2014-03-20

申请号：US13684578

申请日：2012-11-26

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang

IPC: H01L23/48 ,  H01L21/32

CPC classification number: H01L21/4857 ,  H01L21/32 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81449 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2224/8148 ,  H01L2924/12042 ,  H01L2924/381 ,  H05K1/113 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4682 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/016 ,  H05K2203/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings are respectively filled with the conductive structures. Each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part. Each of the connection parts is connected to the corresponding pad part and the corresponding protruding part. Each of the protruding parts has a curved surface that protrudes from the second surface. A process for fabricating the circuit substrate is also provided.

Abstract translation: 电路基板包括电介质层和多个导电结构。 电介质层具有多个导电开口，第一表面和与第一表面相对的第二表面。 每个导电开口连接第一表面和第二表面。 导电开口分别填充有导电结构。 导电结构中的每一个都是整体形成的，并且包括衬垫部分，连接部分和突出部分。 每个连接部分连接到对应的垫部分和相应的突出部分。 每个突出部分具有从第二表面突出的弯曲表面。 还提供了一种用于制造电路基板的工艺。

公开(公告)号：US20240006400A1

公开(公告)日：2024-01-04

申请号：US17856965

申请日：2022-07-02

Applicant: Intel Corporation

Inventor： Kyle J. Arrington ,  Karumbu Nathan Meyyappan ,  Srikant Nekkanty

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13105 ,  H01L2224/13139 ,  H01L2224/13169 ,  H01L2224/13144 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/81405 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2924/01008 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L24/29

Abstract: In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate. The integrated circuit die includes metal pillars extending from a bottom side of the die facing the top side of the substrate, and the metal pillars of the integrated circuit die are electrically connected to the electrical connectors of the substrate via a liquid metal (e.g., a Gallium-based alloy).

公开(公告)号：US09324580B2

公开(公告)日：2016-04-26

申请号：US14789998

申请日：2015-07-02

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/48 ,  H01L21/32 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H01L21/32 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81449 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2224/8148 ,  H01L2924/12042 ,  H01L2924/381 ,  H05K1/113 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4682 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/016 ,  H05K2203/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed.

Abstract translation: 提供了一种用于制造电路基板的工艺。 该过程包括以下步骤。 提供载体。 导电层和电介质层被放置在载体上，并且导电层位于载体和电介质层之间。 图案化电介质层以形成具有部分暴露导电层的第一开口的图案化电介质层。 在导电层的暴露部分上形成弧形槽。 形成具有分别连接第一开口的第二开口的第一图案化光致抗蚀剂层。 形成导电结构，其中每个导电结构一体地形成，并且包括衬垫部分，连接部分和突出部分; 第二开口，第一开口和弧形槽分别填充有垫部分，连接部分和突出部分。 去除第一图案化光致抗蚀剂层，载体和导电层。

公开(公告)号：US20120126418A1

公开(公告)日：2012-05-24

申请号：US12954397

申请日：2010-11-24

Applicant: Chien-Te Feng ,  Shih-Chin Lin

Inventor： Chien-Te Feng ,  Shih-Chin Lin

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/481 ,  H01L23/4985 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81418 ,  H01L2224/8142 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/8146 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2224/81473 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/83385 ,  H01L2224/85409 ,  H01L2224/85411 ,  H01L2224/85413 ,  H01L2224/85416 ,  H01L2224/85418 ,  H01L2224/8542 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/85457 ,  H01L2224/8546 ,  H01L2224/85463 ,  H01L2224/85464 ,  H01L2224/85469 ,  H01L2224/85473 ,  H01L2224/85476 ,  H01L2224/85478 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit (IC) device includes a polymer substrate having a topside surface and a bottomside surface opposite the topside surface, a plurality of through-holes that extend from the topside surface to the bottomside surface, and a plurality of bottom metal pads on the bottomside surface positioned over the plurality of through-holes. At least one IC die having an active topside including a plurality of bond pads and a second side is affixed to the topside surface. Bonding features are coupled to the plurality of bond pads for coupling respective ones of the plurality of bond pads to the plurality bottom metal pads. The bonding features extend into the through-holes to contact the bottom metal pads.

Abstract translation: 集成电路（IC）装置包括具有顶侧表面和与顶侧表面相对的底部表面的聚合物基板，从顶侧表面延伸到底部表面的多个通孔，以及多个底部金属焊盘 底部表面定位在多个通孔上。 具有包括多个接合焊盘的活动顶面和第二侧的至少一个IC管芯固定到顶侧表面。 接合特征耦合到多个接合焊盘，用于将多个接合焊盘中的相应接合焊盘连接到多个底部金属焊盘。 接合特征延伸到通孔中以接触底部金属焊盘。

公开(公告)号：US09984993B2

公开(公告)日：2018-05-29

申请号：US15294508

申请日：2016-10-14

Applicant: Advanced Semiconductor, Inc.

Inventor： Min-Fong Shu ,  Yi-Hsiu Tseng ,  Kuan-Neng Chen ,  Shu-Chiao Kuo

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/1182 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13623 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13663 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13676 ,  H01L2224/13678 ,  H01L2224/13687 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81096 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81898 ,  H01L2224/83104 ,  H01L2224/83193 ,  H01L2224/92125 ,  H01L2924/00015 ,  H01L2924/15311 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/8109 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053

Abstract: A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.

公开(公告)号：US20160240503A1

公开(公告)日：2016-08-18

申请号：US14622494

申请日：2015-02-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Min-Fong Shu ,  Yi-Hsiu TSENG ,  Kuan-Neng CHEN ,  Shu-Chiao KUO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/1182 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13623 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13663 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13676 ,  H01L2224/13678 ,  H01L2224/13687 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81096 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81898 ,  H01L2224/83104 ,  H01L2224/83193 ,  H01L2224/92125 ,  H01L2924/00015 ,  H01L2924/15311 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/8109 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053

Abstract: The present disclosure relates to bonding structures useful in semiconductor packages and methods of manufacturing the same. In an embodiment, the bonding structure comprises a substrate, having a top surface and including at least one bonding pad, wherein each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface; and a semiconductor element including at least one pillar, wherein each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.

Abstract translation: 本公开涉及可用于半导体封装的结合结构及其制造方法。 在一个实施例中，接合结构包括具有顶表面并且包括至少一个焊盘的衬底，其中每个接合焊盘邻近衬底的顶表面设置并具有倾斜表面; 以及包括至少一个柱的半导体元件，其中每个柱结合到相应焊盘的倾斜表面的一部分，并且在所述柱的侧壁和相应的焊盘的倾斜表面之间形成间隙。

公开(公告)号：US20150303074A1

公开(公告)日：2015-10-22

申请号：US14789998

申请日：2015-07-02

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang

IPC: H01L21/48 ,  H05K3/42 ,  H01L21/683

CPC classification number: H01L21/4857 ,  H01L21/32 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81449 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2224/8148 ,  H01L2924/12042 ,  H01L2924/381 ,  H05K1/113 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4682 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/016 ,  H05K2203/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed.

Abstract translation: 提供了一种用于制造电路基板的工艺。 该过程包括以下步骤。 提供载体。 导电层和电介质层被放置在载体上，并且导电层位于载体和电介质层之间。 图案化电介质层以形成具有部分暴露导电层的第一开口的图案化电介质层。 在导电层的暴露部分上形成弧形槽。 形成具有分别连接第一开口的第二开口的第一图案化光致抗蚀剂层。 形成导电结构，其中每个导电结构一体地形成，并且包括衬垫部分，连接部分和突出部分; 第二开口，第一开口和弧形槽分别填充有垫部分，连接部分和突出部分。 去除第一图案化光致抗蚀剂层，载体和导电层。