公开(公告)号：US20160066427A1

公开(公告)日：2016-03-03

申请号：US14610910

申请日：2015-01-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/157 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/83

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a recess; disposing an electronic element in the recess of the carrier; forming an insulating layer in the recess to encapsulate the electronic element; forming a circuit structure on the carrier, wherein the circuit structure is electrically connected to the electronic element; forming a plurality of through holes penetrating the carrier; and forming a conductive material in the through holes to form a plurality of conductors, wherein the conductors are electrically connected to the circuit structure. By using the carrier as a substrate body, the present invention avoids warping of the package structure.

Abstract translation: 提供一种制造封装结构的方法，其包括以下步骤：提供具有凹槽的载体; 将电子元件设置在载体的凹部中; 在所述凹部中形成绝缘层以封装所述电子元件; 在所述载体上形成电路结构，其中所述电路结构电连接到所述电子元件; 形成穿过所述载体的多个通孔; 以及在所述通孔中形成导电材料以形成多个导体，其中所述导体电连接到所述电路结构。 通过使用载体作为基板本体，本发明避免了封装结构的翘曲。

公开(公告)号：US09196596B2

公开(公告)日：2015-11-24

申请号：US14013469

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Wei-Jen Chang ,  Hsien-Wen Chen

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/64 ,  H01L24/67 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A method of manufacturing an interposer is provided, including forming a plurality of first openings on one surface side of a substrate, forming a first metal layer in the first openings, forming on the other surface side of the substrate a plurality of second openings that are in communication with the first openings, forming a second metal layer in the second openings, and electrically connecting the first metal layer to the second metal layer, so as to form conductive through holes. The conductive through holes are formed stage by stage, such that the fabrication time in forming the metal layers is reduced, and a metal material will not be accumulated too thick on a surface of the substrate. Therefore, the metal material has a smoother surface, and no overburden will be formed around end surfaces of the through holes. An interposer is also provided.

Abstract translation: 提供一种制造插入件的方法，包括在基板的一个表面侧上形成多个第一开口，在第一开口中形成第一金属层，在基板的另一表面侧上形成多个第二开口， 与所述第一开口连通，在所述第二开口中形成第二金属层，并且将所述第一金属层电连接到所述第二金属层，以形成导电通孔。 导电通孔逐级形成，使得形成金属层的制造时间减少，并且金属材料在基板的表面上不会太累积。 因此，金属材料具有更平滑的表面，并且在通孔的端面周围不会形成覆盖层。 还提供了插入器。

公开(公告)号：US10249562B2

公开(公告)日：2019-04-02

申请号：US14610910

申请日：2015-01-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a recess; disposing an electronic element in the recess of the carrier; forming an insulating layer in the recess to encapsulate the electronic element; forming a circuit structure on the carrier, wherein the circuit structure is electrically connected to the electronic element; forming a plurality of through holes penetrating the carrier; and forming a conductive material in the through holes to form a plurality of conductors, wherein the conductors are electrically connected to the circuit structure. By using the carrier as a substrate body, the present invention avoids warping of the package structure.

公开(公告)号：US09748183B2

公开(公告)日：2017-08-29

申请号：US15455704

申请日：2017-03-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Cheng-Hao Ciou ,  Cheng-Chieh Wu ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

公开(公告)号：US20170186703A1

公开(公告)日：2017-06-29

申请号：US15455704

申请日：2017-03-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Cheng-Hao Ciou ,  Cheng-Chieh Wu ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/82

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

公开(公告)号：US20170040248A1

公开(公告)日：2017-02-09

申请号：US14817233

申请日：2015-08-04

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Sheng-Li Lu ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/92144 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A met of fabricating an electronic package is provided, g: providing a carrier body haying a first surface formed with a plurality of recessed portions, and a second surface opposing the first surface and interconnecting with the recessed portions; forming on the first surface of the carrier body an electronic structure that has a plurality of conductive elements received in the recessed portions correspondingly; and removing a portion of the carrier body, with the conductive elements exposed from the second surface of the carrier body. Therefore, the carrier body is retained, and the fabrication cost is reduced since no temporary material is required. The present invention further provides the electronic package thus fabricated.

Abstract translation: 提供了一种制造电子封装的方法，其特征在于，提供一种载体，该载体体形成有形成有多个凹部的第一表面，以及与该第一表面相对的第二表面，并与该凹部相互连接。 在所述载体主体的第一表面上形成相应地具有容纳在所述凹部中的多个导电元件的电子结构; 以及从载体主体的第二表面露出的导电元件去除载体主体的一部分。 因此，由于不需要临时材料，因此保持了承载体，并且制造成本降低。 本发明还提供如此制造的电子封装。

公开(公告)号：US20160086903A1

公开(公告)日：2016-03-24

申请号：US14672268

申请日：2015-03-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/15153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/03

Abstract: The present invention provides a semiconductor structure and a method of fabricating the same. The semiconductor structure includes a carrier, a semiconductor chip and an encapsulant. The semiconductor chip is disposed on the carrier, and has opposing non-active and active surfaces. The non-active surface is coupled to the carrier, and the active surface has a plurality of metallic pillars formed thereon. A under bump metallogy layer is formed between the metallic pillars and the active surface and on side surfaces of the metal pillars. The surface of the encapsulant is flush with end surfaces of the metallic pillars. Therefore, the product yield is increased significantly.

Abstract translation: 本发明提供一种半导体结构及其制造方法。 半导体结构包括载体，半导体芯片和密封剂。 半导体芯片设置在载体上，并且具有相对的非活性和有效表面。 非活性表面耦合到载体，并且活性表面上形成有多个金属柱。 在金属柱和活性表面之间以及金属柱的侧表面上形成凸块下金属层。 密封剂的表面与金属柱的端面齐平。 因此，产品产量明显增加。

公开(公告)号：US20160049359A1

公开(公告)日：2016-02-18

申请号：US14744289

申请日：2015-06-19

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ching-Wen Chiang ,  Kuang-Hsin Chen ,  Hsien-Wen Chen

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: An interposer is provided, including a substrate body, a plurality of conductive posts formed in the substrate body, and a plurality of conductive pads formed on the substrate body and electrically connected to the conductive posts. The conductive pads and the conductive posts are integrally formed. As such, no interface is formed between the conductive pads and the conductive posts, thereby preventing delamination or cracking from occurring between the conductive pads and the conductive posts.

Abstract translation: 提供了一种插入器，包括基板主体，形成在基板主体中的多个导电柱，以及形成在基板主体上并电连接到导电柱的多个导电焊盘。 导电焊盘和导电柱一体形成。 因此，在导电焊盘和导电柱之间没有形成界面，从而防止在导电焊盘和导电柱之间发生分层或破裂。

公开(公告)号：US09076796B2

公开(公告)日：2015-07-07

申请号：US13894687

申请日：2013-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Hung Lin ,  Chun-Hung Lu ,  Guang-Hwa Ma ,  Hsiao-Chun Huang ,  Kuang-Hsin Chen

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/53295 ,  H01L21/76802 ,  H01L21/76808 ,  H01L23/49894 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnection structure for a package is disclosed. The interconnection structure includes a substrate body having a conductive portion formed on a surface thereof; a first photosensitive dielectric layer formed on the surface of the substrate body and having a via for exposing the conductive potion; a conductive via formed in the via; a second photosensitive dielectric layer formed on the first photosensitive dielectric layer and having a opening for exposing the conductive via and a portion of the first photosensitive dielectric layer; and a conductive trace layer formed in the opening of the second photosensitive dielectric layer so as to be electrically connected to the conductive portion through the conductive via, thereby simplifying the fabrication process and reducing the fabrication cost and time.

Abstract translation: 公开了一种用于封装的互连结构。 互连结构包括在其表面上形成有导电部分的基板主体; 形成在所述基板主体的表面上并且具有用于使所述导电部暴露的通孔的第一光敏介电层; 在通孔中形成的导电通孔; 形成在所述第一光敏介电层上并具有用于使所述导电通孔和所述第一光敏介电层的一部分暴露的开口的第二光敏介电层; 以及形成在第二感光介电层的开口中的导电迹线层，以便通过导电通孔电连接到导电部分，从而简化制造工艺并降低制造成本和时间。

公开(公告)号：US20140117538A1

公开(公告)日：2014-05-01

申请号：US13949557

申请日：2013-07-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Kuang-Hsin Chen ,  Chun-Hung Lu

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19105

Abstract: A fabrication method of a package structure is provided, which includes the steps of: providing an interposer having a plurality of recess holes; forming a conductive bump in a lower portion of each of the recess holes; forming a conductive through hole on the conductive bump in each of the recess holes; removing a portion of the interposer so as for the conductive bumps to protrude from the interposer; and mounting at least a first external element on the conductive bumps, thereby simplifying the fabrication process, shortening the process time and reducing the material cost.

Abstract translation: 提供一种封装结构的制造方法，其包括以下步骤：提供具有多个凹陷孔的插入件; 在每个凹槽的下部形成导电凸块; 在每个凹孔中的导电凸块上形成导电通孔; 去除所述插入件的一部分，以使所述导电凸起从所述插入件突出; 并且至少将第一外部元件安装在导电凸块上，从而简化制造工艺，缩短处理时间并降低材料成本。