公开(公告)号：US20150102484A1

公开(公告)日：2015-04-16

申请号：US14136238

申请日：2013-12-20

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD

Inventor： Chia-Cheng Chen ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Liang-yi Hung ,  Wei-chung Hsiao ,  Yu-cheng Pai ,  Shih-Chao Chiu ,  Don-Son Jiang ,  Yi-Feng Chang ,  Lung-Yuan Wang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/535

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1011 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H05K1/181 ,  H05K1/183 ,  H05K3/284 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging.

Abstract translation: 公开了一种封装结构，其包括：第一基板; 形成在第一基板上并电连接到第一基板并具有空腔的积聚层; 至少电子元件设置在所述空腔中并电连接到所述第一基板; 堆叠构件，其设置在堆积层上以堆叠在第一基板上; 以及形成在堆积层和堆叠构件之间的密封剂。 堆积层有助于实现隔离效应并防止焊料桥接。

公开(公告)号：US20220068801A1

公开(公告)日：2022-03-03

申请号：US17101277

申请日：2020-11-23

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: An electronic package is provided, in which an electronic structure used as an integrated voltage regulator and a plurality of conductive pillars are embedded in an encapsulating layer to facilitate electrical transmission with electronic components at a close range.

公开(公告)号：US20180211925A1

公开(公告)日：2018-07-26

申请号：US15492394

申请日：2017-04-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Lung-Yuan Wang

IPC: H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L21/52 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/561 ,  H01L21/563 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/014

Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US20180138158A1

公开(公告)日：2018-05-17

申请号：US15867910

申请日：2018-01-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Hao Tung ,  Chang-Yi Lan ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Shu-Huei Huang

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/207

Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.

公开(公告)号：US20160233205A1

公开(公告)日：2016-08-11

申请号：US15134037

申请日：2016-04-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Chi Hsu ,  Chia-Kai Shih ,  Shu-Huei Huang

IPC: H01L25/00 ,  H01L25/10 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.

Abstract translation: 提供一种制造半导体封装的方法，其包括以下步骤：提供在其表面上具有多个第一导电柱的第一衬底，并提供第二衬底，该第二衬底具有设置在其上的芯片的第三表面和与其相对的第四表面 到第三面; 通过第一导电柱将第一衬底设置在第二衬底的第三表面上; 在所述第一基板和所述第二基板之间形成密封剂，其中所述密封剂具有与所述第一基板相邻的第一表面和与所述第一表面相对的第二表面; 并移除第一基板，从而有效地防止焊料桥接发生。

公开(公告)号：US20150041972A1

公开(公告)日：2015-02-12

申请号：US14249626

申请日：2014-04-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Kai Shih ,  Lung-Yuan Wang ,  Cheng-Chia Chiang ,  Chu-Chi Hsu ,  Shih-Hao Tung

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L24/97 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor package is disclosed, which includes: a first substrate; a first semiconductor component disposed on the first substrate; a second substrate disposed on the first semiconductor component and electrically connected to the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate and encapsulating the first semiconductor component and the conductive elements. The present invention can control the height and volume of the conductive elements since the distance between the first substrate and the second substrate is fixed by bonding the second substrate to the first semiconductor component.

Abstract translation: 公开了一种半导体封装，其包括：第一衬底; 设置在所述第一基板上的第一半导体部件; 第二基板，设置在所述第一半导体部件上，并且通过多个导电元件电连接到所述第一基板; 以及形成在第一基板和第二基板之间并封装第一半导体部件和导电元件的第一密封剂。 本发明可以控制导电元件的高度和体积，因为通过将第二基板结合到第一半导体部件来固定第一基板和第二基板之间的距离。

公开(公告)号：US12283560B2

公开(公告)日：2025-04-22

申请号：US18413887

申请日：2024-01-16

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.

公开(公告)号：US12114427B2

公开(公告)日：2024-10-08

申请号：US17831301

申请日：2022-06-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Wen-Liang Lien

IPC: H05K3/32 ,  H01L23/31 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/144 ,  H01L23/3157 ,  H05K1/111 ,  H05K1/181 ,  H05K3/32 ,  H05K3/4682 ,  H05K1/0203 ,  H05K2201/042

Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.

公开(公告)号：US11382214B2

公开(公告)日：2022-07-05

申请号：US16589663

申请日：2019-10-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Yuan Wang ,  Wen-Liang Lien

IPC: H05K1/14 ,  H05K1/11 ,  H05K1/18 ,  H01L23/31 ,  H05K3/32 ,  H05K1/02

Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.

公开(公告)号：US20220068867A1

公开(公告)日：2022-03-03

申请号：US17102841

申请日：2020-11-24

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Feng Kao ,  Lung-Yuan Wang

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.