公开(公告)号：US09265154B2

公开(公告)日：2016-02-16

申请号：US14461828

申请日：2014-08-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Chi-Ching Ho ,  Ying-Chou Tsai

IPC: H01L21/8242 ,  H05K1/18 ,  H05K1/11 ,  H05K3/10 ,  H01L49/02

CPC classification number: H05K1/186 ,  H01L23/49822 ,  H01L23/50 ,  H01L28/40 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/10 ,  H05K3/42 ,  H05K2201/10015 ,  H05K2203/0733 ,  H01L2924/00

Abstract: A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.

Abstract translation: 提供一种封装基板的制造方法，其包括以下步骤：在载体上形成第一导电部分; 在每个第一导电部分上依次形成导电柱和取向层; 在载体上形成密封剂，用于封装第一导电部分，导电柱和对准层; 在所述密封剂中的每个取向层上形成导电孔，并在所述导电通孔和所述密封剂上形成第二导电部分; 并移除载体。 每个第一导电部分和相应的导电柱，对准层和导电通孔形成导电结构。 取向层具有大于导电柱和导电通孔的垂直投影面积，从而减小导电柱和导电通孔的尺寸，从而增加布线密度和电子元件安装密度。

公开(公告)号：US12068535B2

公开(公告)日：2024-08-20

申请号：US17748957

申请日：2022-05-19

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Shao-Tzu Tang ,  Chih-Hsien Chiu ,  Wen-Jung Tsai ,  Ko-Wei Chang ,  Chia-Chu Lai

IPC: H01Q1/48 ,  H01Q1/38 ,  H01Q1/50

CPC classification number: H01Q1/48 ,  H01Q1/38 ,  H01Q1/50

Abstract: An antenna module is provided with a plurality of antenna structures and a shielding structure arranged on a plate body, and the shielding structure is located between two adjacent antenna structures, where the shielding structure includes a concave portion formed on the plate body and a dielectric material formed between the concave portion and the antenna structure to generate different impedance characteristics, thereby improving the antenna isolation.

公开(公告)号：US09991197B2

公开(公告)日：2018-06-05

申请号：US15632669

申请日：2017-06-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chi-Ching Ho ,  Shao-Tzu Tang ,  Yu-Che Liu ,  Ying-Chou Tsai

IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2224/13099 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

公开(公告)号：US20180068896A1

公开(公告)日：2018-03-08

申请号：US15704388

申请日：2017-09-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Chang-Yi Lan ,  Ying-Chou Tsai

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/568 ,  H01L22/12 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00015 ,  H01L2924/1816 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/20 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/81

Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.

公开(公告)号：US09805979B2

公开(公告)日：2017-10-31

申请号：US14624642

申请日：2015-02-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Chang-Yi Lan ,  Ying-Chou Tsai

IPC: H01L23/28 ,  H01L21/78 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/568 ,  H01L22/12 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00015 ,  H01L2924/1816 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/20 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/81

Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.

公开(公告)号：US20170273185A1

公开(公告)日：2017-09-21

申请号：US15615158

申请日：2017-06-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Ying-Chou Tsai

IPC: H05K3/00 ,  H05K1/11

CPC classification number: H05K3/0014 ,  H05K1/116 ,  H05K2201/09118 ,  H05K2201/09545 ,  H05K2201/09563 ,  Y10T29/49167

Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.

公开(公告)号：US20140091462A1

公开(公告)日：2014-04-03

申请号：US13729963

申请日：2012-12-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chia-Cheng Chen ,  Chi-Ching Ho ,  Shao-Tzu Tang ,  Yu-Che Liu ,  Ying-Chou Tsai

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2224/13099 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

Abstract translation: 提供一种半导体封装，其包括：由用于制造积层层结构的材料制成的电介质层; 形成在电介质层上的导电迹线层; 半导体芯片安装在导电迹线层上并电连接到导电迹线层上; 以及形成在电介质层上以封装半导体芯片和导电迹线层的密封剂。 由于在电介质层和导电迹线层之间形成牢固的接合，因此本发明能够防止电介质层与导电迹线层之间的分层发生，从而提高可靠性，并且通过现有的制造方法便于封装小型化。