公开(公告)号：US09842758B2

公开(公告)日：2017-12-12

申请号：US14836613

申请日：2015-08-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi

IPC: H01L21/00 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L25/10

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/295 ,  H01L24/19 ,  H01L25/105 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1041

Abstract: A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles.

公开(公告)号：US09666536B2

公开(公告)日：2017-05-30

申请号：US14956758

申请日：2015-12-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Wei Liu ,  Yan-Heng Chen ,  Mao-Hua Yeh ,  Hung-Wen Liu ,  Yi-Che Lai

IPC: H01L21/4763 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/31053 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311

Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

公开(公告)号：US20160190099A1

公开(公告)日：2016-06-30

申请号：US14956758

申请日：2015-12-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Wei Liu ,  Yan-Heng Chen ,  Mao-Hua Yeh ,  Hung-Wen Liu ,  Yi-Che Lai

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/00 ,  H01L21/78 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L23/5389 ,  H01L21/31053 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311

Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

Abstract translation: 本发明提供一种封装结构及其制造方法。 该方法包括提供具有金属层的第一载体; 在所述金属层上形成电介质层; 形成嵌入介电层并从电介质层的表面突出的多个导电柱，并在电介质层的表面上设置电子部件; 在所述电介质层上形成封装层以包围所述多个导电柱，所述电介质层和所述电子部件; 去除封装层和第一载体的一部分，使得多个导电柱中的每一个的两端从封装层和电介质层露出。 因此，本发明有效地降低了制造成本，并且可以消除在制造导电柱的过程中对打开过程的需要。

公开(公告)号：US20160111359A1

公开(公告)日：2016-04-21

申请号：US14862457

申请日：2015-09-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

Abstract translation: 提供一种制造电子封装的方法，其包括以下步骤：提供至少具有嵌入其中的电子元件的绝缘层; 在所述绝缘层的一侧上形成至少第一通孔; 在绝缘层的第一通孔中形成第一导体; 在所述绝缘层上形成电连接到所述电子元件和所述第一导体的第一电路结构; 以及在所述绝缘层的另一侧上形成第二通孔，其中所述第二通孔与所述第一通孔连通。 这样，第二通孔和第一通孔构成通孔。 由于通孔通过两个步骤制造，所以可以根据实际需要调整通孔的纵横比（深度/宽度），以提高工艺成品率。

公开(公告)号：US08828796B1

公开(公告)日：2014-09-09

申请号：US14085168

申请日：2013-11-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Yuan Chi ,  Wei-Yu Chen ,  Hung-Wen Liu ,  Yan-Heng Chen ,  Hsi-Chang Hsu

IPC: H01L21/44 ,  H01L23/02 ,  H01L23/498

CPC classification number: H01L23/5383 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor package and a method of manufacturing the same are provided, the semiconductor package including a first package unit having a first encapsulant and a first semiconductor element, a second package unit having a second encapsulant and a second semiconductor element, a supporting member interposed between the first and second encapsulant, a plurality of conductors penetrating the first encapsulant, the supporting member and the second encapsulant, and redistribution structures disposed on the first and second encapsulants, wherein the first and second encapsulants are coupled with each other by the supporting member to provide sufficient support and protection to enhance the structure strength of the first and second package units.

Abstract translation: 提供一种半导体封装及其制造方法，所述半导体封装包括具有第一密封剂和第一半导体元件的第一封装单元，具有第二密封剂的第二封装单元和第二半导体元件， 所述第一和第二密封剂，穿过所述第一密封剂，所述支撑构件和所述第二密封剂的多个导体以及设置在所述第一和第二密封剂上的再分配结构，其中所述第一和第二密封剂通过所述支撑构件彼此联接， 提供足够的支撑和保护以增强第一和第二包装单元的结构强度。

公开(公告)号：US20160126126A1

公开(公告)日：2016-05-05

申请号：US14836613

申请日：2015-08-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/027 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/295 ,  H01L24/19 ,  H01L25/105 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1041

Abstract: A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles.

Abstract translation: 提供一种制造封装结构的方法，包括以下步骤：在载体上设置具有面向载体的有源表面的半导体芯片; 在载体上形成图案化的抗蚀剂层; 在载体上形成暴露半导体芯片的非活性表面和图案化抗蚀剂层的表面的密封剂; 并移除载体以获得包装结构。 此后，可以在封装结构的相对侧上形成再分布层，并且可以通过钻孔在图案化的抗蚀剂层中形成多个通孔，从而允许在通孔中形成用于电气的多个导电通孔 连接包装结构的相对侧上的再分布层。 因此，本发明克服了通过直接钻削具有填料颗粒的密封剂引起的通孔的表面粗糙度的常规缺陷。

公开(公告)号：US20150325508A1

公开(公告)日：2015-11-12

申请号：US14584428

申请日：2014-12-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chung-Tang Lin ,  Chieh-Yuan Chi

IPC: H01L23/498 ,  H05K1/02 ,  H01L21/56

CPC classification number: H01L21/48 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0298 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/014

Abstract: A carrier structure is provided, which includes: a metal oxide plate having opposite first and second surfaces and a plurality of through holes penetrating the first and second surfaces; a plurality of conductive portions formed in the through holes, respectively; and a plurality of conductive pads formed on the first surface of the metal oxide plate, wherein each of the conductive pads is correspondingly positioned on and in contact with a plurality of the conductive portions so as to be electrically connected to the plurality of the conductive portions. By replacing a conventional silicon interposer with the metal oxide plate, the present invention eliminates the need to form through silicon vias as required in the prior art and therefore simplifies the fabrication process.

Abstract translation: 提供一种载体结构，其包括：具有相对的第一和第二表面的金属氧化物板和穿过第一和第二表面的多个通孔; 分别形成在通孔中的多个导电部分; 以及形成在金属氧化物板的第一表面上的多个导电焊盘，其中每个导电焊盘相应地定位在多个导电部分上并与多个导电部分接触，以便电连接到多个导电部分 。 通过用金属氧化物板替代传统的硅插入器，本发明消除了如现有技术中所需要通过硅通孔形成的需要，因此简化了制造工艺。

公开(公告)号：US09117698B2

公开(公告)日：2015-08-25

申请号：US14449278

申请日：2014-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Jung-Pang Huang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu ,  Guang-Hwa Ma

IPC: H01L21/56 ,  H01L23/48 ,  H01L21/02 ,  H01L21/50 ,  H01L29/84 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L23/538

CPC classification number: H01L24/11 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/033 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/48227 ,  H01L2224/81 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.

Abstract translation: 半导体封装包括：具有相反的第一和第二表面的电介质层; 嵌入在介电层中并具有多个电极焊盘的半导体芯片; 分别设置在半导体芯片的电极焊盘上的多个第一金属柱，使得第一金属柱的顶端从第一表面露出; 至少第二金属柱穿透介电层，使得第二金属柱的两个相对端分别从第一表面和第二表面露出; 第一电路层，形成在第一表面上，用于电连接第一和第二金属柱; 以及形成在所述第二表面上用于电连接所述第二金属柱的第二电路层。 该半导体封装省去了用于在模塑料中形成导电柱的常规激光烧蚀和电镀工艺，从而节省制造时间和成本。

公开(公告)号：US20140342507A1

公开(公告)日：2014-11-20

申请号：US14449278

申请日：2014-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Jung-Pang Huang ,  Hsin-Yi Liao ,  Shih-Kuang Chiu ,  Guang-Hwa Ma

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/033 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1412 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/48227 ,  H01L2224/81 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost.

Abstract translation: 半导体封装包括：具有相反的第一和第二表面的电介质层; 嵌入在介电层中并具有多个电极焊盘的半导体芯片; 分别设置在半导体芯片的电极焊盘上的多个第一金属柱，使得第一金属柱的顶端从第一表面露出; 至少第二金属柱穿透介电层，使得第二金属柱的两个相对端分别从第一表面和第二表面露出; 第一电路层，形成在第一表面上，用于电连接第一和第二金属柱; 以及形成在所述第二表面上用于电连接所述第二金属柱的第二电路层。 该半导体封装省去了用于在模塑料中形成导电柱的常规激光烧蚀和电镀工艺，从而节省制造时间和成本。

公开(公告)号：US20140342506A1

公开(公告)日：2014-11-20

申请号：US14146171

申请日：2014-01-02

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi ,  Hung-Wen Liu

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.

Abstract translation: 本发明公开了一种制造半导体封装的方法，包括提供具有绝缘层和至少嵌入绝缘层中的半导体元件的封装单元，其中半导体元件从绝缘层露出，并且形成在多个凹部中 绝缘层; 并且将再分布结构电连接到半导体元件。 凹陷部分的形成释放绝缘层的应力并防止绝缘层发生翘曲。