利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

24 条记录 (耗时 0.019 秒)

    Apparatus and method for an integrated high-performance electrical interconnect
    11.
    发明授权
    Apparatus and method for an integrated high-performance electrical interconnect 有权
    集成高性能电气互连的装置和方法

    公开(公告)号：US06809260B1

    公开(公告)日：2004-10-26

    申请号：US10667847

    申请日：2003-09-22

    申请人： Victor Prokofiev

    发明人： Victor Prokofiev

    IPC分类号： H05K702

    CPC分类号： H05K1/141 ,  H05K1/145 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10522 ,  H05K2201/10734

    摘要： According to some embodiments, an integrated high-quality printed circuit board is provided. For example, a first integrated circuit device may be mounted on both a first printed circuit board and a second printed circuit board (e.g., a polyimide film having better dielectric characteristics as compared to the first board). A second integrated circuit device may be located remote from the first integrated circuit device and may also be mounted on both the first and second boards.

    摘要翻译： 根据一些实施例，提供集成的高质量印刷电路板。 例如，第一集成电路器件可以安装在第一印刷电路板和第二印刷电路板（例如，与第一板相比具有更好的介电特性的聚酰亚胺膜）上。 第二集成电路装置可以位于远离第一集成电路装置的位置，并且也可以安装在第一和第二板上。

    Packaged substrate having variable width conductors and a variably spaced reference plane
    14.
    发明申请
    Packaged substrate having variable width conductors and a variably spaced reference plane 审中-公开
    封装衬底具有可变宽度的导体和可变间隔的参考平面

    公开(公告)号：US20060001149A1

    公开(公告)日：2006-01-05

    申请号：US10883049

    申请日：2004-06-30

    申请人： Victor Prokofiev

    发明人： Victor Prokofiev

    IPC分类号： H01L23/48

    CPC分类号： H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A package substrate for a microelectronic die is described. The package substrate has first terminals in a small area and second terminals in a larger area with conductors connecting the first and second terminals. The conductors are fairly narrow near the first terminals so that they can fit next to one another near the first terminals and before fanning out to the second terminals. The reference plane next to the conductors forms a step so that a first surface of the reference plane is closer to the conductors where they are narrow, and a second portion of the reference plane surrounding the first portion is further from the conductors where they are wider. The capacitance created between a respective conductor and the reference plane remains relatively constant per unit length because the reference plane is closer to the conductor where the conductor is narrow and further from the conductor where the conductor is wider.

    摘要翻译： 描述了用于微电子管芯的封装衬底。 封装衬底具有小面积的第一端子和具有连接第一和第二端子的导体的较大区域中的第二端子。 导体在第一端子附近相当窄，使得它们可以在第一端子附近彼此相邻并且在扇形到第二端子之前。 靠近导体的参考平面形成一个步骤，使得参考平面的第一表面更靠近导体，其中它们较窄，并且围绕第一部分的参考平面的第二部分远离导体，其中它们较宽 。 由于参考平面更靠导体导体较窄的导体，导体较宽的导体，所以在相应的导体与参考平面之间产生的电容保持相对恒定。

    USING POWER DIVIDING MATCHING NODES TO OPTIMIZE INTERCONNECTS
    15.
    发明申请
    USING POWER DIVIDING MATCHING NODES TO OPTIMIZE INTERCONNECTS 审中-公开
    使用功率分配匹配节点优化互连

    公开(公告)号：US20130007327A1

    公开(公告)日：2013-01-03

    申请号：US13173959

    申请日：2011-06-30

    申请人： Victor Prokofiev

    发明人： Victor Prokofiev

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4086 ,  G06F1/26

    摘要： Systems and methods of improving computing system interconnects may involve providing an upstream channel and a plurality of downstream channels. A passive matching node can be connected to the upstream channel and the downstream channels, wherein the matching node is configured to couple power between the upstream memory channel and the downstream channels. The matching node may also perform impedance matching as well as isolate two or more signals on the downstream channels from one another. In one example, the matching node includes a power divider/combiner.

    摘要翻译： 改进计算系统互连的系统和方法可以包括提供上行信道和多个下行信道。 无源匹配节点可以连接到上游信道和下游信道，其中匹配节点被配置为在上游存储器信道和下行信道之间耦合电力。 匹配节点还可以执行阻抗匹配以及将下游信道上的两个或更多个信号彼此隔离。 在一个示例中，匹配节点包括功率分配器/组合器。

    Capacitor device and method
    17.
    发明授权
    Capacitor device and method 失效
    电容器件及方法

    公开(公告)号：US06795296B1

    公开(公告)日：2004-09-21

    申请号：US10677083

    申请日：2003-09-30

    申请人： Cengiz A. Palanduz ,  Victor Prokofiev

    发明人： Cengiz A. Palanduz ,  Victor Prokofiev

    IPC分类号： H01G406

    CPC分类号： H01G4/1227 ,  C04B35/4682 ,  C04B35/62805 ,  C04B2235/32 ,  C04B2235/3206 ,  C04B2235/3208 ,  C04B2235/3224 ,  C04B2235/3227 ,  C04B2235/3251 ,  C04B2235/3272 ,  C04B2235/3279 ,  H01G4/33 ,  Y10T29/43

    摘要： A method for making, and a dielectric material is provided. A capacitor is provided that includes a lossy dielectric layer that is also not leaky. The lossy behavior dampens unwanted oscillations in power supplies or other electrical systems. A capacitor is further provided is tunable for an amount of lossy behavior over a broad range. A core dopant concentration can be varied, and a doped core grain fraction can be varied to control the extent of a desired lossy property in a capacitor. Dielectric materials having grains with doped shells reduce leakiness. Additionally in selected embodiments, undoped core grains mixed with doped core grains reduce leakiness.

    摘要翻译： 提供了制造方法和电介质材料。 提供了一种电容器，其包括也不漏的有损介质层。 有损行为会抑制电源或其他电气系统中的不必要的振荡。 进一步提供的电容器可在一个宽范围内调节一定量的有损行为。 可以改变芯掺杂剂浓度，并且可以改变掺杂的芯晶粒分数以控制电容器中期望的有损性质的程度。 具有掺杂壳的晶粒的介电材料减少泄漏。 另外在选择的实施例中，与掺杂的芯颗粒混合的未掺杂的芯晶粒减少泄漏。