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11.发明授权Universal IO connector and interface capable of both wired and wireless operation 有权通用IO连接器和能够进行有线和无线操作的接口公开(公告)号：US09312908B2
公开(公告)日：2016-04-12
申请号：US13995592
申请日：2011-11-11
申请人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper , Debabani Choudhury , Frank T. Hady
发明人： Stephen R. Mooney , Howard L. Heck , James E. Jaussi , Bryan K. Casper , Debabani Choudhury , Frank T. Hady
CPC分类号： H04B1/40 , G06F13/4068 , G06F2213/0042
摘要： Systems and methods of interconnecting devices may include a connector assembly having a substrate, a set of input/output (IO) contacts, an antenna structure and transceiver logic. In one example, the transceiver logic may process one or more IO signals associated with the antenna structure and process one or more IO signals associated with the set of IO contacts.
摘要翻译： 互连设备的系统和方法可以包括具有基板，一组输入/输出（IO）触点，天线结构和收发器逻辑的连接器组件。 在一个示例中，收发器逻辑可以处理与天线结构相关联的一个或多个IO信号并且处理与该组IO触点相关联的一个或多个IO信号。
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公开(公告)号：US20140357128A1
公开(公告)日：2014-12-04
申请号：US13997096
申请日：2011-12-14
CPC分类号： H01R24/64 , H01R12/721 , H01R13/66 , H01R13/6658 , H01R24/28 , H01R24/62 , H01R2107/00
摘要： Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
摘要翻译： 方法和系统可以包括具有集成缓冲器的输入/输出（IO）接口，壳体和设置在壳体内的基板。 衬底可以包括第一侧，第二侧和连接边缘。 集成缓冲器可以耦合到衬底的第一侧和第二侧中的至少一个。 多个触点列可以耦合到衬底的第一侧。 每排触点可以基本上平行于连接边缘堆叠。 衬底可以具有耦合到其上的功率输出，并且集成缓冲器可以包括具有耦合到功率输出的电源输出的电压调节器。
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公开(公告)号：US20140197696A1
公开(公告)日：2014-07-17
申请号：US13995594
申请日：2011-10-17
CPC分类号： G06F13/385 , G06F1/266 , H01H9/54 , H01R13/6658 , Y10T307/74
摘要： Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.
摘要翻译： 互连设备的系统和方法可以包括具有电压调节器，一个或多个信令电路，第一组触点，连接到一个或多个信号电路的第二组触点和逻辑电路的输入/输出（IO）连接器组件 接收配置命令。 如果配置命令对应于第一协议，逻辑还可以将第一组触点连接到电压调节器。 如果配置命令对应于第二协议，另一方面，逻辑可以将第一组联系人连接到一个或多个信令电路。
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公开(公告)号：US09106217B2
公开(公告)日：2015-08-11
申请号：US13977050
申请日：2011-12-06
CPC分类号： H03K19/0008 , H01R12/722 , H01R12/727 , H01R13/6658 , H01R24/60 , H01R25/006 , H03K19/0175
摘要： Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.
摘要翻译： 公开了具有多个托架并且包括围绕多对基板的壳体的可伸缩输入/输出接口。 一对基板中的第一基板可以具有第一接触表面，并且该对基板的第二基板可以具有与第一接触表面相对的第二接触表面，其中每个基板具有连接边缘。 至少一个集成缓冲器可以耦合到每个衬底的第一侧或第二侧。 可以将多排触点耦合到一对基板的每个基板的相对表面，其中每排触点可以基本上平行于连接边缘堆叠。 每个连接边缘也可以耦合到单独的集成缓冲器。
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公开(公告)号：US20140184270A1
公开(公告)日：2014-07-03
申请号：US13977050
申请日：2011-12-06
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K19/0008 , H01R12/722 , H01R12/727 , H01R13/6658 , H01R24/60 , H01R25/006 , H03K19/0175
摘要： Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.
摘要翻译： 公开了具有多个托架并且包括围绕多对基板的壳体的可伸缩输入/输出接口。 一对基板中的第一基板可以具有第一接触表面，并且该对基板的第二基板可以具有与第一接触表面相对的第二接触表面，其中每个基板具有连接边缘。 至少一个集成缓冲器可以耦合到每个衬底的第一侧或第二侧。 可以将多排触点耦合到一对基板的每个基板的相对表面，其中每排触点可以基本上平行于连接边缘堆叠。 每个连接边缘也可以耦合到单独的集成缓冲器。
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公开(公告)号：US20140182914A1
公开(公告)日：2014-07-03
申请号：US13727701
申请日：2012-12-27
申请人： Kuan-Yu Chen , Howard L. Heck
发明人： Kuan-Yu Chen , Howard L. Heck
CPC分类号： H05K1/11 , H01R12/57 , H01R12/58 , H05K1/025 , H05K1/0269 , H05K1/0271 , H05K1/111 , H05K1/115 , H05K2201/094 , H05K2201/09409 , H05K2201/10189 , H05K2201/10659 , H05K2201/2045 , H05K2203/163 , Y10T29/49124
摘要： A universal serial bus hybrid footprint design is described herein. The design includes an outer row of one or more surface mount technology (SMT) contacts and an inner row of one or more printed through holes (PTH). The hybrid footprint design enables a data through put of at least 10 Gbps.
摘要翻译： 本文描述了通用串行总线混合覆盖设计。 该设计包括一排或多个表面贴装技术（SMT）触点和一列或多个印刷通孔（PTH）的内排。 混合足迹设计能够通过至少10 Gbps的数据进行数据传输。
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公开(公告)号：US5301118A
公开(公告)日：1994-04-05
申请号：US793981
申请日：1991-11-18
申请人： Howard L. Heck , John S. Kresge
发明人： Howard L. Heck , John S. Kresge
CPC分类号： G06F17/18 , G06F17/5009 , G06F2217/10
摘要： A two-stage Monte Carlo method of tolerancing components of an assembly is provided. Statistical measures of component features are not time invariant, but change over a production run. That is, the mean value of component feature measures and the standard distribution of the component feature measures about the time dependent mean are not invariant over a production run, but shift with time and throughput. According to the invention, these "shifted" or "adjusted" parameters are utilized in a Monte Carlo simulation to determine discrete values for the individual points of each output distribution, x(i), y(i), z(i). The individual points of the output distributions, x(i), y(i), z(i), are combined in a second Monte Carlo simulation step for individual assembly final fit F(x(i), y(i), z(i)). The statistics of the individual assembly final fits are then compared to manufacturing specifications.
摘要翻译： 提供了一种用于组装组件公差的两阶段蒙特卡罗方法。 组件特征的统计测量不是时间不变的，而是改变生产运行。 也就是说，组件特征量度的平均值和关于时间依赖平均值的组件特征量度的标准分布在生产运行中不是不变的，而是随时间和吞吐量而变化。 根据本发明，在蒙特卡罗模拟中使用这些“移位”或“调整”参数来确定每个输出分布x（i），y（i），z（i）的各个点的离散值。 输出分布x（i），y（i），z（i）的各个点在用于单独组合最终拟合F（x（i），y（i），z）的第二蒙特卡罗模拟步骤中组合 （一世））。 然后将各组装最终配合的统计数据与制造规范进行比较。
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18.发明申请公开(公告)号：US20200006246A1
公开(公告)日：2020-01-02
申请号：US16402522
申请日：2019-05-03
IPC分类号： H01L23/552 , H01L23/16 , H01L23/538 , H01L23/00 , H01L25/10 , H01L21/48 , H01L25/00
摘要： A stiffener includes an integrated cable-header recess that couples a semiconductor package substrate flexible cable. The flexible cable connects to a device on a board without using interconnections that are arrayed through the board. A semiconductive die is coupled to the semiconductor package substrate and flexible cable through the cable-header recess.
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公开(公告)号：US06672902B2
公开(公告)日：2004-01-06
申请号：US10017456
申请日：2001-12-12
申请人： Harry G. Skinner , Steve Y. Chang , Howard L. Heck , Yun Ji
发明人： Harry G. Skinner , Steve Y. Chang , Howard L. Heck , Yun Ji
IPC分类号： H01R13648
CPC分类号： H01R13/6596 , H01R13/6598
摘要： A system includes a chassis having at least one wall, the chassis housing electrical components and a layer of flexible foam electromagnetic interference (EMI) emission absorption material covering an interior surface of the wall. A system also includes a chassis containing slots, the chassis housing electrical components and a layer of flexible foam electromagnetic interference (EMI) emission absorption material covering at least one of the slots.
摘要翻译： 一种系统包括具有至少一个壁的底盘，底盘容纳电气部件和覆盖壁的内表面的柔性泡沫电磁干扰（EMI）发射吸收材料层。 系统还包括容纳槽的底盘，所述底盘容纳电气部件和覆盖至少一个所述槽的柔性泡沫电磁干扰（EMI）发射吸收材料层。
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公开(公告)号：US5384690A
公开(公告)日：1995-01-24
申请号：US97544
申请日：1993-07-27
申请人： Charles R. Davis , Thomas P. Duffy , Steven L. Hanakovic , Howard L. Heck , John T. Kolias , John S. Kresge , David N. Light , Ajit K. Trivedi
发明人： Charles R. Davis , Thomas P. Duffy , Steven L. Hanakovic , Howard L. Heck , John T. Kolias , John S. Kresge , David N. Light , Ajit K. Trivedi
IPC分类号： H01R4/26 , H01R4/58 , H01R12/61 , H01R13/66 , H05K1/00 , H05K1/03 , H05K1/14 , H05K3/00 , H05K3/32 , H05K3/46 , H01R23/68
CPC分类号： H05K3/4635 , H01R12/613 , H01R13/665 , H05K3/462 , H01R4/26 , H01R4/58 , H05K1/0373 , H05K1/0393 , H05K2201/015 , H05K2201/0154 , H05K2201/09109 , H05K2201/09536 , H05K2201/10159 , H05K3/328 , H05K3/4623 , H05K3/4641 , Y10S428/901 , Y10T29/49126 , Y10T29/49128 , Y10T29/49179 , Y10T428/24917
摘要： Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.
摘要翻译： 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。 各个子组件的层压是通过与要层压的区域中的子组件之间的全氟化碳聚合物化学相容（可粘合）化学相容的低熔点粘合剂，以及任选的与化学不相容的高熔点掩模 可粘合到）在不想层压的区域中的子组件之间的全氟化碳聚合物。 加热组件叠层以选择性地在要层压的区域中进行粘合和层压，同时避免在不想层压的区域中层压。
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