公开(公告)号：US08519462B2

公开(公告)日：2013-08-27

申请号：US13169864

申请日：2011-06-27

Applicant: Yih Wang ,  M. Clair Webb ,  Nick Lindert ,  Swaminathan Sivakumar ,  Kevin X. Zhang ,  Dinesh Somasekhar

Inventor： Yih Wang ,  M. Clair Webb ,  Nick Lindert ,  Swaminathan Sivakumar ,  Kevin X. Zhang ,  Dinesh Somasekhar

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/0207 ,  H01L27/10891

Abstract: A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.

Abstract translation: 描述了具有成对单元的6F2 DRAM单元。 在一个实施例中，单元对由具有限定虚拟字线的门的n型隔离晶体管分开。 虚拟字线由具有有利于p沟道器件的功函数的金属制成。

公开(公告)号：US07981756B2

公开(公告)日：2011-07-19

申请号：US12317656

申请日：2008-12-22

Applicant: Nick Lindert ,  Brian Doyle ,  Dinesh Somasekhar ,  Christopher J. Jezewski ,  Swaminathan Sivakumar ,  Kevin Zhang ,  Stephen Wu

Inventor： Nick Lindert ,  Brian Doyle ,  Dinesh Somasekhar ,  Christopher J. Jezewski ,  Swaminathan Sivakumar ,  Kevin Zhang ,  Stephen Wu

IPC: H01L21/20

CPC classification number: H01L27/101 ,  H01L28/90

Abstract: A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.

Abstract translation: 形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。 该过程包括将电容器单元边界的第一高度降低到第二高度。 普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。

公开(公告)号：US20090001431A1

公开(公告)日：2009-01-01

申请号：US11821971

申请日：2007-06-26

Applicant: Nadia Rahhal-Orabi ,  Charles H. Wallace ,  Alison Davis ,  Swaminathan Sivakumar

Inventor： Nadia Rahhal-Orabi ,  Charles H. Wallace ,  Alison Davis ,  Swaminathan Sivakumar

IPC: H01L29/78 ,  H01L21/4763

CPC classification number: H01L21/76804 ,  H01L21/76816 ,  H01L29/78

Abstract: In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.

Abstract translation: 在本发明的一个实施例中，接触图案化可以被分成两个或更多遍，这可以允许设计者相对独立于接触顶部临界尺寸来控制栅极高度临界尺寸。

公开(公告)号：US20070218685A1

公开(公告)日：2007-09-20

申请号：US11384143

申请日：2006-03-17

Applicant: Swaminathan Sivakumar ,  Charles Wallace ,  Alison Davis ,  Nadia Rahhal-Orabi

Inventor： Swaminathan Sivakumar ,  Charles Wallace ,  Alison Davis ,  Nadia Rahhal-Orabi

IPC: H01L21/44

CPC classification number: H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/485

Abstract: A method to form transistor contacts begins with providing a transistor that includes a gate stack and first and second diffusion regions formed on a substrate, and a dielectric layer formed atop the gate stack and the diffusion regions. A first photolithography process forms first and second diffusion trench openings for the first and second diffusion regions. A sacrificial layer is then deposited into the first and second diffusion trench openings. Next, a second photolithography process forms a gate stack trench opening for the gate stack and a local interconnect trench opening coupling the gate stack trench opening to the first diffusion trench opening. The second photolithography process is carried out independent of the first photolithography process. The sacrificial layer is then removed and a metallization process is carried out to fill the first and second diffusion trench openings, the gate stack trench opening, and the local interconnect trench opening with a metal layer.

Abstract translation: 形成晶体管触点的方法开始于提供一种晶体管，该晶体管包括栅极堆叠以及形成在衬底上的第一和第二扩散区域，以及形成在栅极堆叠和扩散区域顶部的电介质层。 第一光刻工艺形成用于第一和第二扩散区域的第一和第二扩散沟槽开口。 然后将牺牲层沉积到第一和第二扩散沟槽开口中。 接下来，第二光刻工艺形成用于栅极堆叠的栅极堆叠沟槽开口和将栅极堆叠沟槽开口耦合到第一扩散沟槽开口的局部互连沟槽开口。 第二光刻工艺是独立于第一光刻工艺进行的。 然后去除牺牲层，并且进行金属化处理以填充第一和第二扩散沟槽开口，栅极堆叠沟槽开口和具有金属层的局部互连沟槽开口。

公开(公告)号：US07265431B2

公开(公告)日：2007-09-04

申请号：US10150197

申请日：2002-05-17

Applicant: Swaminathan Sivakumar

Inventor： Swaminathan Sivakumar

IPC: H01L31/0232 ,  H01L31/06

CPC classification number: G03F7/095 ,  G03F7/091 ,  H01L21/0276

Abstract: A semiconductor wafer may be coated with an imageable anti-reflective coating. As a result, the coating may be removed using the same techniques used to remove overlying photoresists. This may overcome the difficulty of etching anti-reflective coatings using standard etches because of their poor selectivity to photoresist and the resulting propensity to cause integrated circuit defects arising from anti-reflective coating remnants.

Abstract translation: 可以用可成像的抗反射涂层涂覆半导体晶片。 结果，可以使用用于去除覆盖的光致抗蚀剂的相同技术去除涂层。 这可以克服使用标准蚀刻来蚀刻抗反射涂层的难度，因为它们对光致抗蚀剂的选择性差，并导致由抗反射涂层残留物引起集成电路缺陷的倾向。

公开(公告)号：US20070128526A1

公开(公告)日：2007-06-07

申请号：US11297209

申请日：2005-12-07

Applicant: Charles Wallace ,  Shannon Daviess ,  Swaminathan Sivakumar

Inventor： Charles Wallace ,  Shannon Daviess ,  Swaminathan Sivakumar

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F1/36

Abstract: Sub-resolution assist features for non-collinear features are described for use in photolithography. A photolithography mask with elongated features is synthesized. An end-to-end gap between two features if found for which the ends of the two features facing the gap are linearly offset from one another. A sub-resolution assist feature is applied to the end-to-end gap between the elongated features, and the synthesized photolithography mask is modified to include the sub-resolution assist feature.

Abstract translation: 描述了非共线特征的子分辨率辅助功能，用于光刻。 合成具有细长特征的光刻掩模。 如果发现两个特征面对间隙的两端的端部彼此线性偏移，则两个特征之间的端对端间隙。 子分辨率辅助特征被应用于细长特征之间的端到端间隙，并且合成的光刻掩模被修改为包括子分辨率辅助特征。

公开(公告)号：US20050148180A1

公开(公告)日：2005-07-07

申请号：US10750200

申请日：2003-12-30

Applicant: Swaminathan Sivakumar ,  Curtis Ward ,  Timothy Hehr ,  Mark Fradkin

Inventor： Swaminathan Sivakumar ,  Curtis Ward ,  Timothy Hehr ,  Mark Fradkin

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768 ,  H01L23/04 ,  H01L23/485

CPC classification number: H01L21/76804 ,  H01L21/0335 ,  H01L21/31144 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention relates to exposing a bond pad on a substrate. A bond pad is formed over a silicon substrate with the subsequent formation of a dielectric over the bond pad. A patterned resist is formed, and at least opening is processed to form a sloped sidewall profile. The sloped sidewall profile is subsequently etched and transferred to the dielectric layer, exposing the bond pad.

公开(公告)号：US10211088B2

公开(公告)日：2019-02-19

申请号：US15743616

申请日：2015-09-10

Applicant: INTEL CORPORATION ,  Charles H. Wallace ,  Swaminathan Sivakumar

Inventor： Charles H. Wallace ,  Elliot N. Tan ,  Paul A. Nyhus ,  Swaminathan Sivakumar

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L23/528 ,  H01L21/033

Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.

公开(公告)号：US09530688B2

公开(公告)日：2016-12-27

申请号：US14822865

申请日：2015-08-10

Applicant: Paul A. Nyhus ,  Swaminathan Sivakumar ,  Robert Bristol

Inventor： Paul A. Nyhus ,  Swaminathan Sivakumar ,  Robert Bristol

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.

公开(公告)号：US20140053117A1

公开(公告)日：2014-02-20

申请号：US13997565

申请日：2011-12-30

Applicant: Paul A. Nyhus ,  Shem O. Ogadhoh ,  Swaminathan Sivakumar ,  Seongtae Jeong

Inventor： Paul A. Nyhus ,  Shem O. Ogadhoh ,  Swaminathan Sivakumar ,  Seongtae Jeong

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G03F1/36 ,  G03F1/70 ,  G06F17/5068

Abstract: Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.

Abstract translation: 提供了用于确定制造光刻掩模的相位区域的厚度或深度的技术。 一个示例性实施例提供了一种方法，其包括：提供包括第一测试集的第一掩模布局设计，以及提供包括第二测试集的第二掩模布局设计，其中所述第二测试集大于所述第一测试集; 通过针对一系列相位深度/厚度的第一测试集合中关注的结构的焦点来模拟关键尺寸，并且基于模拟结果选择初始优选的掩模相位深度/厚度; 并且以最初的优选相位深度/厚度生成快速厚掩模模型（FTM），并且使用FTM校正第二掩模布局设计的第二测试集，由此提供优化的掩模布局设计。 可以实施具有优化的掩模布局设计的掩模以给出最佳图案化。