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公开(公告)号：US10720387B2
公开(公告)日：2020-07-21
申请号：US15078387
申请日：2016-03-23
发明人： Hsiao-Tsung Yen , Cheng-Wei Luo
IPC分类号： H01L23/522 , H01L25/065 , H01L21/822 , H01L27/06 , H01L23/48 , H01L23/66
摘要： A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first conductive line and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first substrate. The first conductive line is over the first shielding layer. The first IMD layer is between the first substrate and the first conductive line.
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公开(公告)号：US09754874B2
公开(公告)日：2017-09-05
申请号：US14062924
申请日：2013-10-25
发明人： Hsiao-Tsung Yen , Cheng-Wei Luo
IPC分类号： H01L21/8234 , H01L21/8244 , H01L23/522 , H01L21/822 , H01L23/66 , H01L27/06 , H01L25/065
CPC分类号： H01L23/5227 , H01L21/8221 , H01L23/481 , H01L23/5223 , H01L23/5225 , H01L23/5226 , H01L23/66 , H01L25/065 , H01L25/0657 , H01L27/0694 , H01L2223/6622 , H01L2225/06527 , H01L2225/06537 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： An inductive capacitive structure including a first substrate, a first conductive line over the first substrate, a first shielding layer over the first substrate and a second substrate over the first substrate.
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公开(公告)号：US09653531B2
公开(公告)日：2017-05-16
申请号：US14514212
申请日：2014-10-14
发明人： Hsiao-Tsung Yen , Min-Chie Jeng , Hsien-Pin Hu , Tzuan-Horng Liu , Chin-Wei Kuo , Chung-Yu Lu , Yu-Ling Lin
IPC分类号： H01L49/02 , H01L23/64 , H01L23/498 , H01L23/522 , H01L21/768 , H01L25/065 , H01L23/00
CPC分类号： H01L28/10 , H01L21/76885 , H01L23/49822 , H01L23/5227 , H01L23/645 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/81192 , H01L2224/81801 , H01L2224/83192 , H01L2224/83862 , H01L2225/06513 , H01L2225/06527 , H01L2924/1206 , H01L2924/19042 , H01L2924/00014
摘要： A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line.
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14.发明申请公开(公告)号：US20160358871A1
公开(公告)日：2016-12-08
申请号：US15238520
申请日：2016-08-16
发明人： Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
CPC分类号： H01L24/11 , H01L24/10 , H01L24/15 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/023 , H01L2224/03 , H01L2224/13147 , H01L2224/81815 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.
摘要翻译： 集成电路封装包括管芯。 导电层包括管芯中的再分配层（RDL），或管芯上方的微凸起层，或两者。 微凸起层包括至少一个微凸起线。 滤波器包括导电层。 电容器包括形成在导电层中的电极。
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公开(公告)号：US09449917B2
公开(公告)日：2016-09-20
申请号：US14720805
申请日：2015-05-24
发明人： Cheng-Wei Luo , Hsiao-Tsung Yen , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号： H01L29/00 , H01L23/522 , H01L21/48 , H01L23/14 , H01L23/498 , H01L23/538 , H01F17/00 , H01L49/02 , H01F27/28
CPC分类号： H01L23/5227 , H01F17/0033 , H01F2017/0066 , H01F2017/0086 , H01F2027/2809 , H01L21/486 , H01L23/147 , H01L23/49816 , H01L23/49822 , H01L23/5384 , H01L28/10 , H01L2224/16225 , H01L2224/16235 , H01L2924/13091 , H01L2924/15311 , H01L2924/00
摘要： In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
摘要翻译： 根据实施例，半导体器件包括半导体管芯，插入件和将半导体管芯接合到插入件的导电凸块。 半导体管芯包括第一金属化层，第一金属化层包括第一导电图案。 插入器包括第二金属化层，并且第二金属化层包括第二导电图案。 一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。 磁性层位于线圈内。 在另一个实施例中，线圈形成在单个基板上，其中磁性层位于线圈内。 其他实施例考虑了线圈，电感器和/或变压器的其他配置，并考虑了制造方法。
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公开(公告)号：US09362613B2
公开(公告)日：2016-06-07
申请号：US13789040
申请日：2013-03-07
发明人： Hsiao-Tsung Yen
CPC分类号： H01Q1/36 , H01L2224/48227 , H01P11/001 , H01Q7/00 , H01Q9/00 , Y10T29/49016
摘要： An antenna structure includes a substrate having at least one first pad for wire bonding. A chip is mounted on the substrate, and the chip has at least one second pad for wire bonding. At least one bond wire connects the at least one first pad and the at least one second pad. The at least one bond wire is configured to transmit or receive an electromagnetic wave signal in at least one specified frequency for data communication.
摘要翻译： 天线结构包括具有至少一个用于引线接合的第一焊盘的衬底。 芯片安装在基板上，芯片具有至少一个用于引线接合的第二焊盘。 至少一个接合线连接至少一个第一焊盘和至少一个第二焊盘。 所述至少一个接合线被配置为以至少一个指定频率发送或接收用于数据通信的电磁波信号。
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公开(公告)号：US09330830B2
公开(公告)日：2016-05-03
申请号：US14659821
申请日：2015-03-17
发明人： Hsiao-Tsung Yen , Yu-Ling Lin , Ying-Ta Lu , Huan-Neng Chen , Ho-Hsiang Chen
IPC分类号： H01L23/00 , H01F27/28 , H01L23/522 , H01F5/00 , H01L23/528 , H01L49/02
CPC分类号： H01F27/2804 , H01F5/003 , H01F2027/2809 , H01L23/5226 , H01L23/5227 , H01L23/528 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors.
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公开(公告)号：US09324720B2
公开(公告)日：2016-04-26
申请号：US14528809
申请日：2014-10-30
发明人： Hsiao-Tsung Yen , Yu-Ling Lin
IPC分类号： H01L21/8234 , H01L27/108 , H01L27/06 , H01L23/522 , H01L49/02 , H01L23/528 , H01L29/06 , H01L27/08
CPC分类号： H01L27/10808 , H01L21/823475 , H01L23/5226 , H01L23/5228 , H01L23/528 , H01L27/0629 , H01L27/0802 , H01L27/10844 , H01L27/10897 , H01L28/20 , H01L29/0653 , H01L2924/0002 , H01L2924/00
摘要： A method comprises implanting ions in a substrate to form a first active region and a second active region, depositing a first dielectric layer over the substrate, forming a first via and a second via in the first dielectric layer, wherein the first via is over the first active region and the second via is over the second active region, depositing a second dielectric layer over the first dielectric layer, forming a third via and a fourth via in the second dielectric layer, wherein the third via is over the first via and the fourth via is over the second via and forming a connector in a metallization layer over the second dielectric layer, wherein the connector is electrically connected to the third via and the fourth via.
摘要翻译： 一种方法包括在衬底中注入离子以形成第一有源区和第二有源区，在衬底上沉积第一介电层，在第一介电层中形成第一通孔和第二通孔，其中第一通孔位于第 第一有源区和第二通孔在第二有源区上方，在第一介电层上沉积第二电介质层，在第二介电层中形成第三通孔和第四通孔，其中第三通孔位于第一通孔之上， 第四通孔在第二通孔之上，并且在第二电介质层上的金属化层中形成连接器，其中连接器电连接到第三通孔和第四通孔。
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公开(公告)号：US20160035729A1
公开(公告)日：2016-02-04
申请号：US14880965
申请日：2015-10-12
发明人： Hsiao-Tsung Yen , Yu-Ling Lin
IPC分类号： H01L27/108 , H01L23/522 , H01L23/528 , H01L27/06 , H01L29/06
CPC分类号： H01L27/10808 , H01L21/823475 , H01L23/5226 , H01L23/5228 , H01L23/528 , H01L27/0629 , H01L27/0802 , H01L27/10844 , H01L27/10897 , H01L28/20 , H01L29/0653 , H01L2924/0002 , H01L2924/00
摘要： A system comprises a first transistor comprising a first drain/source region and a second drain/source region, a second transistor comprising a third drain/source region and a fourth drain/source region, wherein the first transistor and the second transistor are separated by an isolation region, a first resistor formed by at least two vias, wherein a bottom via of the first resistor is in direct contact with the first drain/source region, a second resistor formed by at least two vias, wherein a bottom via of the second resistor is in direct contact with the second drain/source region, a bit line connected to the third drain/source region through a plurality of bit line contacts and a capacitor connected to the fourth drain/source region through a capacitor contact.
摘要翻译： 一种系统包括：第一晶体管，包括第一漏极/源极区域和第二漏极/源极区域;第二晶体管，包括第三漏极/源极区域和第四漏极/源极区域，其中第一晶体管和第二晶体管被第 隔离区，由至少两个通孔形成的第一电阻器，其中第一电阻器的底部通孔与第一漏极/源极区域直接接触，由至少两个通孔形成的第二电阻器， 第二电阻器与第二漏极/源极区域直接接触，通过多个位线触点连接到第三漏极/源极区域的位线和通过电容器触点连接到第四漏极/源极区域的电容器。
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20.发明申请Slot-Shielded Coplanar Strip-line Compatible with CMOS Processes 审中-公开Slot-Shielded Coplanar Strip-line兼容CMOS工艺公开(公告)号：US20150325513A1
公开(公告)日：2015-11-12
申请号：US14802267
申请日：2015-07-17
发明人： Yu-Ling Lin , Hsiao-Tsung Yen , Ho-Hsiang Chen , Chin-Wei Kuo , Chewn-Pu Jou
IPC分类号： H01L23/522 , H01L23/528 , H01L23/64
CPC分类号： H01L23/5225 , H01L23/5226 , H01L23/528 , H01L23/64 , H01L23/66 , H01L27/0629 , H01L2223/6627 , H01L2924/0002 , H01L2924/00
摘要： A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.
摘要翻译： 带状线包括在衬底上延伸穿过多个电介质层的接地平面; 在基板上并在接地平面的一侧的信号线; 在信号线下方和第一金属层中的第一多个金属条，其中所述第一多个金属条彼此平行并且彼此间隔开; 以及信号线下方的第二多个金属条，并且在第一金属层上方的第二金属层中。 第二多个金属带垂直地与空间重叠。 第一多个金属条通过接地平面电耦合到第二多个金属条，并且不通过物理地接触第一多个金属条和第二多个金属条。
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