公开(公告)号：US11881867B2

公开(公告)日：2024-01-23

申请号：US17467561

申请日：2021-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Narasimhan Rajagopal ,  Eeshan Miglani ,  Chirag Chandrahas Shetty ,  Neeraj Shrivastava ,  Shagun Dusad ,  Srinivas Kumar Reddy Naru ,  Nithin Gopinath ,  Charls Babu ,  Shivam Srivastava ,  Viswanathan Nagarajan ,  Jagannathan Venkataraman ,  Harshit Moondra ,  Prasanth K ,  Visvesvaraya Appala Pentakota

IPC: H03M1/10

CPC classification number: H03M1/1019

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

公开(公告)号：US11777513B2

公开(公告)日：2023-10-03

申请号：US17538746

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Karthikeyan Gunasekaran ,  Snehasish Roychowdhury ,  Rakesh Manjunath ,  Aswath V S ,  Sthanunathan Ramakrishnan ,  Sarma Sudareswara Gunturi ,  Rahul Sharma ,  Jagannathan Venkataraman ,  Nagarajan Viswanathan

IPC: H03M1/10 ,  H03M1/66 ,  H03M1/06 ,  H03M1/08

CPC classification number: H03M1/1033 ,  H03M1/0631 ,  H03M1/0863 ,  H03M1/662

Abstract: A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.

公开(公告)号：US11309903B1

公开(公告)日：2022-04-19

申请号：US17131981

申请日：2020-12-23

Applicant: Texas Instruments Incorporated

Inventor： Eeshan Miglani ,  Visvesvaraya Appala Pentakota ,  Jagannathan Venkataraman

IPC: H03M1/56 ,  H03M1/06 ,  H03M1/50 ,  H03M1/38

Abstract: A dynamic voltage-to-delay device may have voltage lines for receiving input signals during reset phases, and a current source, connected to the first and second voltage lines, for increasing voltages on the voltage lines during active phases. The voltage-to-delay device may also have comparators, connected to the voltage lines, for generating first and second output signals during the active phases when the voltages on the voltage lines reach a threshold voltage, such that a delay between the output signals is representative of a difference between voltages of the input signals. The voltage-to-delay device may have at least two current sources. The comparators may have a tail node to which a voltage is applied during a reset phase, and a current source for reducing the voltage at the tail node, and thereby reducing a threshold voltage during an active phase.

公开(公告)号：US11303312B2

公开(公告)日：2022-04-12

申请号：US17112137

申请日：2020-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara Gunturi ,  Jagannathan Venkataraman ,  Jawaharlal Tangudu ,  Narasimhan Rajagopal ,  Eeshan Miglani

IPC: H04B1/10 ,  H04B1/40 ,  H03G3/30 ,  H04B1/12

Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.

公开(公告)号：US11063793B1

公开(公告)日：2021-07-13

申请号：US16876308

申请日：2020-05-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ani Xavier ,  Jagannathan Venkataraman ,  Sandeep Oswal

IPC: H04L27/01 ,  H04L25/03

Abstract: An equalization circuit includes a feed-forward equalization (FFE) circuit and a decision feedback equalization (DFE) circuit. The FFE circuit includes a first FFE tap, a second FFE tap coupled to the first FFE tap, and a variable gain amplifier. The variable gain amplifier includes an input and a programmable capacitor. The input is coupled to the first FFE tap and the second FFE tap. The programmable capacitor is coupled to the input. The DFE circuit includes an input and a DFE tap. The input is coupled to the variable gain amplifier. The DFE tap is coupled to the input of the variable gain amplifier.

公开(公告)号：US10985769B2

公开(公告)日：2021-04-20

申请号：US16828149

申请日：2020-03-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Reddy Patukuri ,  Jagannathan Venkataraman ,  Shagun Dusad

IPC: H03M1/08 ,  H04B1/40 ,  H03M1/10

Abstract: A transceiver system includes a clock generator and an analog-to-digital circuit (ADC). The transceiver system also includes a coupling correction circuit coupled to the clock generator and to the ADC, wherein the coupling correction circuit is configured to provide an in-phase correction and a quadrature-phase correction to a signal received by the ADC.

公开(公告)号：US10581451B2

公开(公告)日：2020-03-03

申请号：US15950690

申请日：2018-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan Venkataraman ,  Prabu Sankar Thirugnanam ,  Raja Reddy Patukuri ,  Sandeep Kesrimal Oswal

IPC: H03M3/00

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

公开(公告)号：US10193586B1

公开(公告)日：2019-01-29

申请号：US15859443

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jagannathan Venkataraman ,  Eeshan Miglani

IPC: H04B1/10 ,  H04B1/16 ,  H03D7/12 ,  H03F3/45 ,  H03K3/017 ,  H03M1/12 ,  H03F3/19

Abstract: A direct conversion radio frequency receiver comprising: a clock generator to provide a first clock signal and a second clock signal; a first node; a second node; a zero-intermediate frequency (zero-IF) mixer coupled to the first and second nodes, clocked by the first and second clock signals, and comprising a first transimpedance amplifier and a second transimpedance amplifier to provide a direct-conversion voltage; a current injector, coupled to the first and second nodes, configurable to inject into the first and second nodes a common mode current or a differential mode current; and a controller, coupled to the zero-IF mixer and the current injector, to adjust at least one of the first and second transimpedance amplifiers based on the direct-conversion voltage when the current injector is to inject the common mode current.

公开(公告)号：US20180214084A1

公开(公告)日：2018-08-02

申请号：US15936029

申请日：2018-03-26

Applicant: Texas Instruments Incorporated

Inventor： Anand Hariraj Udupa ,  Jagannathan Venkataraman ,  Hussam Ahmed ,  Sandeep Kesrimal Oswal

IPC: A61B5/00 ,  A61B5/053

CPC classification number: A61B5/6898 ,  A61B5/053 ,  A61B5/0535 ,  A61B5/0537 ,  A61B5/7221 ,  A61B2560/0468

Abstract: The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source coupled between a first set of input switches. An impedance network is coupled between the first set of input switches and a first set of output switches. The impedance network includes a body impedance and a plurality of electrode impedances. A sense circuit is coupled to the first set of output switches. The sense circuit measures the body impedance and at least one electrode impedance of the plurality of electrode impedances.

公开(公告)号：US20160329906A1

公开(公告)日：2016-11-10

申请号：US14852104

申请日：2015-09-11

Applicant: Texas Instruments Incorporated

Inventor： Raja Reddy PATUKURI ,  Jagannathan Venkataraman ,  Prabu Sankar Thirugnanam

IPC: H03M1/12 ,  G01S7/486 ,  G01S17/02

CPC classification number: G01S7/4865 ,  G01S7/4863 ,  G01S17/89 ,  H03M1/00 ,  H03M1/1245 ,  H03M1/1295 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides a circuit. The circuit includes a first analog to digital converter (ADC) that generates a coarse output in response to a first input and a second input. The first ADC generates the coarse output in a differential phase. A pipeline ADC generates a differential signal in response to the coarse output, the first input and the second input. The pipeline ADC generates the differential signal in a common-mode phase. The first ADC generates a common mode signal in the common-mode phase.

Abstract translation: 本公开提供一种电路。 电路包括响应于第一输入和第二输入而产生粗略输出的第一模数转换器（ADC）。 第一个ADC在差分相位产生粗略输出。 流水线ADC响应于粗略输出（第一输入和第二输入）产生差分信号。 流水线ADC在共模相位产生差分信号。 第一个ADC在共模相位产生共模信号。