公开(公告)号：US11616038B2

公开(公告)日：2023-03-28

申请号：US17094723

申请日：2020-11-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick Francis Thompson ,  Christopher Daniel Manack ,  Stefan Herzer ,  Rakshit Agrawal

IPC: H01L23/495 ,  H01L23/00

Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.

公开(公告)号：US20220384375A1

公开(公告)日：2022-12-01

申请号：US17884284

申请日：2022-08-09

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

Abstract: In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.

公开(公告)号：US20210398882A1

公开(公告)日：2021-12-23

申请号：US16904193

申请日：2020-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick Francis Thompson ,  Christopher Daniel Manack ,  Madison Paige Koziol

IPC: H01L23/495

Abstract: A semiconductor package includes a semiconductor die with an active surface and an inactive surface, the active surface including metal pillars providing electrical connections to functional circuitry of the semiconductor die, and a backside metal layer on the inactive surface. The backside metal layer is attached to the inactive surface. The semiconductor package further includes a plurality of leads with each of the leads including an internal leadfinger portion and an exposed portion that includes a bonding portion. Distal ends of the metal pillars are in contact with and electrically coupled to the internal leadfinger portions. The backside metal layer is exposed on an outer surface of the semiconductor package. The bonding portions and the backside metal layer approximately planar to each other.

公开(公告)号：US10833036B2

公开(公告)日：2020-11-10

申请号：US16233841

申请日：2018-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick Francis Thompson ,  Christopher Daniel Manack ,  Stefan Herzer ,  Rakshit Agrawal

IPC: H01L23/495 ,  H01L23/00

Abstract: A semiconductor die includes a substrate and an integrated circuit provided on the substrate and having contacts. An electrically conductive layer is provided on the integrated circuit and defines electrically conductive elements electrically connected to the contacts. Electrically conductive interconnects coupled with respective electrically conductive elements. The electrically conductive interconnects have at least one of different sizes or shapes from one another.

公开(公告)号：US20160379953A1

公开(公告)日：2016-12-29

申请号：US14749219

申请日：2015-06-24

Applicant: Texas Instruments Incorporated

Inventor： Patrick Francis Thompson ,  Jeffrey Alan West ,  Thomas D. Bonifield ,  Fu-Kang Hsu ,  Ching-Lun Hsia

IPC: H01L23/00

CPC classification number: H01L24/48 ,  H01L23/642 ,  H01L24/03 ,  H01L24/05 ,  H01L24/85 ,  H01L2224/03462 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/4554 ,  H01L2924/00015 ,  H01L2224/29099

Abstract: Circuitry is disclosed that includes a first conductive portion of a first die and a first conductive pillar electrically and physically connected to the first conductive portion. The first conductive pillar includes a first conductive pillar surface. A first bond connects the first conductive pillar surface to a first end of a bond wire.

Abstract translation: 公开了包括第一管芯的第一导电部分和与第一导电部分物理电连接的第一导电柱的电路。 第一导电柱包括第一导电柱表面。 第一接合将第一导电柱表面连接到接合线的第一端。

公开(公告)号：US12255115B2

公开(公告)日：2025-03-18

申请号：US18617517

申请日：2024-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel Manack ,  Patrick Francis Thompson ,  Qiao Chen

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US12009280B2

公开(公告)日：2024-06-11

申请号：US17547698

申请日：2021-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rongwei Zhang ,  Woochan Kim ,  Patrick Francis Thompson

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48138 ,  H01L2224/48158

Abstract: An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.

公开(公告)号：US11942386B2

公开(公告)日：2024-03-26

申请号：US17001429

申请日：2020-08-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel Manack ,  Patrick Francis Thompson ,  Qiao Chen

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/315 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/19104

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US11837518B2

公开(公告)日：2023-12-05

申请号：US17003382

申请日：2020-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Todd Wyant ,  Matthew John Sherbin ,  Christopher Daniel Manack ,  Patrick Francis Thompson ,  You Chye How

IPC: H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L23/3185 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/552 ,  H01L21/6836 ,  H01L2221/68336

Abstract: In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

公开(公告)号：US11562949B2

公开(公告)日：2023-01-24

申请号：US16904193

申请日：2020-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick Francis Thompson ,  Christopher Daniel Manack ,  Madison Paige Koziol

IPC: H01L23/495 ,  H01L23/34 ,  H01L23/48 ,  H01L21/00 ,  H05K7/04 ,  H05K7/18 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/28

Abstract: A semiconductor package includes a semiconductor die with an active surface and an inactive surface, the active surface including metal pillars providing electrical connections to functional circuitry of the semiconductor die, and a backside metal layer on the inactive surface. The backside metal layer is attached to the inactive surface. The semiconductor package further includes a plurality of leads with each of the leads including an internal leadfinger portion and an exposed portion that includes a bonding portion. Distal ends of the metal pillars are in contact with and electrically coupled to the internal leadfinger portions. The backside metal layer is exposed on an outer surface of the semiconductor package. The bonding portions and the backside metal layer approximately planar to each other.