公开(公告)号：US10658383B2

公开(公告)日：2020-05-19

申请号：US16519705

申请日：2019-07-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L21/8249 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11578 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US20190221576A1

公开(公告)日：2019-07-18

申请号：US16128103

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kotaro FUJII ,  Yasuhiro Uchiyama ,  Masaru Kito

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a first electrode film, a second electrode film separated from the first electrode film in a first direction, a third electrode film separated from the second electrode film in the first direction, a fourth electrode film separated from the third electrode film in the first direction, and a first and a second semiconductor members extending in the first direction. The second electrode film includes a first conductive portion, an insulating portion, and a second conductive portion arranged along a second direction. The first semiconductor member pierces the first, third and fourth electrode films and the insulating portion of the second electrode film. The second semiconductor member pierces the first, third and fourth electrode films, and the first conductive portion or the second conductive portion of the second electrode film.

公开(公告)号：US10304849B2

公开(公告)日：2019-05-28

申请号：US14960888

申请日：2015-12-07

Applicant: Toshiba Memory Corporation

Inventor： Ryosuke Sawabe ,  Masaru Kito

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device according to an embodiment includes: an insulating layer; a conductive layer stacked above the insulating layer in a first direction, the conductive layer having a second direction as a longitudinal direction and a third direction as a short direction; and a channel semiconductor layer extending in the first direction, and the conductive layer including a recessed portion narrowed in the third direction.

公开(公告)号：US10163931B2

公开(公告)日：2018-12-25

申请号：US15960842

申请日：2018-04-24

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC: H01L27/10 ,  H01L29/51 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/04 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/105 ,  H01L27/11556 ,  H01L27/11551

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US10020320B2

公开(公告)日：2018-07-10

申请号：US15263739

申请日：2016-09-13

Applicant: Toshiba Memory Corporation

Inventor： Hiroshi Nakaki ,  Masaru Kito

IPC: H01L27/00 ,  H01L27/11582 ,  H01L23/373

CPC classification number: H01L27/11582 ,  H01L23/373 ,  H01L28/00

Abstract: According to the embodiment, a semiconductor device includes: a stacked body; a columnar portion, an insulating portion; and wall portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion is provided in the stacked body and extends in a staking direction of the stacked body. The insulating portion is provided around the stacked body and surrounds the stacked body. The wall portion is provided in the insulating portion and is separated from the stacked body. The wall portion extends in the stacking direction and in a first direction crossing the stacking direction.

公开(公告)号：US09929176B2

公开(公告)日：2018-03-27

申请号：US15398230

申请日：2017-01-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masaaki Higuchi ,  Masaru Kito ,  Masao Shingu

IPC: H01L29/788 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/66833 ,  H01L29/7926

Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.

公开(公告)号：US09917095B2

公开(公告)日：2018-03-13

申请号：US15334828

申请日：2016-10-26

Applicant: Toshiba Memory Corporation

Inventor： Naoki Yasuda ,  Masaru Kito

IPC: H01L29/792 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11582 ,  H01L29/51 ,  H01L27/11568 ,  H01L27/11573

CPC classification number: H01L27/1157 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792 ,  H01L29/7926

Abstract: A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film includes a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.

公开(公告)号：US10985173B2

公开(公告)日：2021-04-20

申请号：US15897623

申请日：2018-02-15

Applicant: Toshiba Memory Corporation

Inventor： Masaaki Higuchi ,  Masaru Kito ,  Masao Shingu

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/66 ,  H01L29/792

Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.

公开(公告)号：US20180197878A1

公开(公告)日：2018-07-12

申请号：US15915653

申请日：2018-03-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L27/11582 ,  H01L21/223 ,  H01L21/265 ,  H01L29/49 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L27/11582 ,  H01L21/223 ,  H01L21/265 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US10008510B2

公开(公告)日：2018-06-26

申请号：US14845796

申请日：2015-09-04

Applicant: Toshiba Memory Corporation

Inventor： Takeshi Sonehara ,  Masaru Kito

IPC: H01L27/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate. The semiconductor memory device further comprises first and second control gate electrodes and third and fourth control gate electrodes stacked sequentially above the substrate and first through fourth via contacts connected to these first through fourth control gate electrodes. The third and fourth control gate electrodes face the first and second control gate electrodes. Positions of the first and second via contacts are far from each other. Positions of the third and fourth via contacts are close to each other.