公开(公告)号：US06927136B2

公开(公告)日：2005-08-09

申请号：US10604884

申请日：2003-08-25

Applicant: Hsiang-Lan Lung ,  Kuang-Yeu Hsieh ,  Ruichen Liu ,  Tai-Bor Wu ,  Jiun-Yi Tseng

Inventor： Hsiang-Lan Lung ,  Kuang-Yeu Hsieh ,  Ruichen Liu ,  Tai-Bor Wu ,  Jiun-Yi Tseng

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L21/336

CPC classification number: B82Y10/00 ,  G11C16/0458 ,  G11C2216/06 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7887

Abstract: A non-volatile memory cell is described. The non-volatile memory cell comprises a substrate, a charge-trapping layer, a gate and a source/drain. The charge-trapping layer comprises an insulating layer and metal nano-particles contained therein, wherein the metal nano-particles are formed with thermal dissociation of an oxide of the same metal. The gate is disposed on the charge-trapping layer, and the source/drain is located in the substrate beside the gate.

Abstract translation: 描述非易失性存储单元。 非易失性存储单元包括衬底，电荷俘获层，栅极和源极/漏极。 电荷捕获层包括绝缘层和其中所含的金属纳米颗粒，其中金属纳米颗粒由相同金属的氧化物的热解离形成。 栅极设置在电荷捕获层上，源极/漏极位于栅极旁边的衬底中。

公开(公告)号：US5714285A

公开(公告)日：1998-02-03

申请号：US682475

申请日：1996-07-17

Applicant: Chih-Chiang Tu ,  Jon-Yiew Gan ,  Tai-Bor Wu ,  Chao-Chen Cheng

Inventor： Chih-Chiang Tu ,  Jon-Yiew Gan ,  Tai-Bor Wu ,  Chao-Chen Cheng

IPC: G06F1/20 ,  G03F1/00 ,  G03F1/32 ,  G06F1/04 ,  H01L21/822 ,  H01L27/04 ,  G03F9/00

CPC classification number: G03F1/32

Abstract: An attenuating phase shifting photomask is formed using attenuating phase shifting composite material combining the optical properties of a first material having a high extinction coefficient and a second material having a high index of refraction. The first material is LaNiO.sub.3 and the second material is TiO.sub.2. The first and second materials are combined as a composite of (LaNiO.sub.3).sub.x (TiO.sub.2).sub.1-x to form attenuating phase shifting blanks and masks. Co-deposition of LaNiO.sub.3 and TiO.sub.2 using rf magnetron sputtering is used to form the (LaNiO.sub.3).sub.x (TiO.sub.2).sub.1-x film on a transparent quartz substrate.

Abstract translation: 使用组合具有高消光系数的第一材料和具有高折射率的第二材料的光学特性的衰减相移复合材料形成衰减相移光掩模。 第一种材料是LaNiO3，第二种材料是TiO2。 将第一和第二材料作为（LaNiO 3）x（TiO 2）1-x的复合物组合以形成衰减相变坯料和掩模。 使用rf磁控溅射法共沉积LaNiO3和TiO2，在透明石英衬底上形成（LaNiO3）x（TiO2）1-x薄膜。

公开(公告)号：US07071007B2

公开(公告)日：2006-07-04

申请号：US10313776

申请日：2002-12-06

Applicant: Yuan-Chieh Tseng ,  Chao-Hsiung Wang ,  Tai-Bor Wu

Inventor： Yuan-Chieh Tseng ,  Chao-Hsiung Wang ,  Tai-Bor Wu

IPC: H01L21/00

CPC classification number: H01L28/55

Abstract: A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric layer. An integrated circuit is also provided including a ferroelectric capacitor. The capacitor includes a bottom electrode formed over a substrate and a ferroelectric and platinum thin film nanocomposite dielectric layer formed over the bottom electrode, wherein the nanocomposite layer includes nanoparticles of platinum. A top electrode is formed over the dielectric layer.

Abstract translation: 形成低电压驱动薄膜铁电电容器的方法包括以下步骤：在底部电极上沉​​积铁电和铂薄膜电介质层，对电介质层进行退火，其中形成纳米复合材料层，包括铂纳米颗粒并形成顶部 电极在电介质层上。 还提供了包括铁电电容器的集成电路。 电容器包括形成在衬底上的底部电极和形成在底部电极上的铁电和铂薄膜纳米复合电介质层，其中纳米复合层包括铂纳米颗粒。 在电介质层上形成顶部电极。

公开(公告)号：US20060038214A1

公开(公告)日：2006-02-23

申请号：US11253178

申请日：2005-10-18

Applicant: Yuan-Chieh Tseng ,  Chao-Hsiung Wang ,  Tai-Bor Wu

Inventor： Yuan-Chieh Tseng ,  Chao-Hsiung Wang ,  Tai-Bor Wu

IPC: H01L29/00

CPC classification number: H01L28/55

Abstract: A method of forming a low-voltage drive thin film ferroelectric capacitor includes the steps of depositing a ferroelectric and platinum thin film dielectric layer over a bottom electrode, annealing the dielectric layer, wherein a nanocomposite layer is formed including nanoparticles of platinum and forming a top electrode over the dielectric layer. An integrated circuit is also provided including a ferroelectric capacitor. The capacitor includes a bottom electrode formed over a substrate and a ferroelectric and platinum thin film nanocomposite dielectric layer formed over the bottom electrode, wherein the nanocomposite layer includes nanoparticles of platinum. A top electrode is formed over the dielectric layer.

Abstract translation: 形成低电压驱动薄膜铁电电容器的方法包括以下步骤：在底部电极上沉​​积铁电和铂薄膜电介质层，对电介质层进行退火，其中形成纳米复合材料层，包括铂纳米颗粒并形成顶部 电极在电介质层上。 还提供了包括铁电电容器的集成电路。 电容器包括形成在衬底上的底部电极和形成在底部电极上的铁电和铂薄膜纳米复合电介质层，其中纳米复合层包括铂纳米颗粒。 在电介质层上形成顶部电极。

公开(公告)号：US20050045943A1

公开(公告)日：2005-03-03

申请号：US10604884

申请日：2003-08-25

Applicant: Hsiang-Lan Lung ,  Kuang-Yeu Hsieh ,  Ruichen Liu ,  Tai-Bor Wu ,  Jiun-Yi Tseng

Inventor： Hsiang-Lan Lung ,  Kuang-Yeu Hsieh ,  Ruichen Liu ,  Tai-Bor Wu ,  Jiun-Yi Tseng

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: B82Y10/00 ,  G11C16/0458 ,  G11C2216/06 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7887

Abstract: A non-volatile memory cell is described. The non-volatile memory cell comprises a substrate, a charge-trapping layer, a gate and a source/drain. The charge-trapping layer comprises an insulating layer and metal nano-particles contained therein, wherein the metal nano-particles are formed with thermal dissociation of an oxide of the same metal. The gate is disposed on the charge-trapping layer, and the source/drain is located in the substrate beside the gate.

Abstract translation: 描述非易失性存储单元。 非易失性存储单元包括衬底，电荷俘获层，栅极和源极/漏极。 电荷捕获层包括绝缘层和其中所含的金属纳米颗粒，其中金属纳米颗粒由相同金属的氧化物的热解离形成。 栅极设置在电荷捕获层上，源极/漏极位于栅极旁边的衬底中。

公开(公告)号：US5973589A

公开(公告)日：1999-10-26

申请号：US102553

申请日：1998-06-23

Applicant: Tai-Bor Wu ,  Jyh-Kuang Tsai

Inventor： Tai-Bor Wu ,  Jyh-Kuang Tsai

IPC: H01C7/112 ,  H01C7/10

CPC classification number: H01C7/112

Abstract: Zinc oxide (ZnO) varistors containing vanadium oxide as the principal additive and one or more cobalt oxides and/or manganese oxides additives exhibit excellent nonlinear current-voltage characteristics. Preferably the varistor compositions are capable of being sintered at a temperature of from 900.degree. C. to 950.degree. C. The low-firing capability of the newly developed materials is attractive for the application in the multilayer chip varistor, because it can cofire with the silver (Ag) or palladium/silver (Pd/Ag) internal electrode instead of using the expensive palladium (Pd) or platinum (Pt) metal. With an appropriate combination of ZnO, vanadium oxide (V.sub.2 O.sub.5) and other oxide additives, a varistor sintered at 900.degree. C. for 2 hours is obtained with a nonlinear coefficient>50 and a leakage current

Abstract translation: 含有氧化钒作为主要添加剂的氧化锌（ZnO）变阻器和一种或多种氧化钴和/或氧化锰添加剂表现出极好的非线性电流 - 电压特性。 优选地，压敏电阻组合物能够在900℃至950℃的温度下烧结。新开发的材料的低焙烧能力对于在多层片式压敏电阻中的应用是有吸引力的，因为它可以与 银（Ag）或钯/银（Pd / Ag）内电极，而不是使用昂贵的钯（Pd）或铂（Pt）金属。 通过ZnO，氧化钒（V2O5）和其他氧化物添加剂的合适组合，获得了在900℃烧结2小时的非线性系数，其非线性系数> 50，漏电流<20μA/ cm2。

公开(公告)号：US5667919A

公开(公告)日：1997-09-16

申请号：US682458

申请日：1996-07-17

Applicant: Chih-Chiang Tu ,  Jon-Yiew Gan ,  Tai-Bor Wu ,  Chin-Lung Lin

Inventor： Chih-Chiang Tu ,  Jon-Yiew Gan ,  Tai-Bor Wu ,  Chin-Lung Lin

IPC: G03F1/00 ,  G03F1/32 ,  G03F9/00

CPC classification number: G03F1/32 ,  Y10T428/24868

Abstract: An attenuated Phase Shift Mask (PSM) blank and an attenuated Phase Shift Mask (PSM), and a method by which the attenuated Phase Shift Mask (PSM) blank and the attenuated Phase Shift Mask (PSM) may be formed. To form the attenuated Phase Shift Mask (PSM) blank there is first provided a transparent substrate. Formed upon the transparent substrate is a tantalum-silicon oxide blanket semi-transparent shifter layer which has the formula,Ta.sub.x Si.sub.y O.sub.1-x-ywherein 0.1

Abstract translation: 衰减相移掩模（PSM）空白和衰减的相移掩模（PSM），以及可以形成衰减的相移掩模（PSM）空白和衰减的相移掩模（PSM）的方法。 为了形成衰减相移掩模（PSM）空白，首先提供透明衬底。 形成在透明基板上的是具有以下分子式的钽 - 氧化硅覆盖层半透明移动层：在0.1

公开(公告)号：US09711373B2

公开(公告)日：2017-07-18

申请号：US12550767

申请日：2009-08-31

Applicant: Che-Hao Chang ,  Cheng-Hao Hou ,  Chen-Hua Yu ,  Tai-Bor Wu

Inventor： Che-Hao Chang ,  Cheng-Hao Hou ,  Chen-Hua Yu ,  Tai-Bor Wu

IPC: H01L21/469 ,  H01L21/316 ,  C23C16/02 ,  C23C16/30 ,  C23C16/40 ,  C23C16/455 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51

CPC classification number: H01L21/306 ,  C23C16/0272 ,  C23C16/308 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/30604 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/517

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a substrate, forming an interfacial layer on the substrate by treating the substrate with radicals, and forming a high-k dielectric layer on the interfacial layer. The radicals are selected from the group consisting of hydrous radicals, nitrogen/hydrogen radicals, and sulfur/hydrogen radicals.

公开(公告)号：US20100093184A1

公开(公告)日：2010-04-15

申请号：US12588367

申请日：2009-10-14

Applicant: Tai-Bor Wu ,  Cheng-Hao Hou

Inventor： Tai-Bor Wu ,  Cheng-Hao Hou

IPC: H01L21/316

CPC classification number: H01L21/0228 ,  C23C16/405 ,  C23C16/45534 ,  C23C16/45536 ,  H01L21/02181 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/517

Abstract: A method for making a metal oxide layer includes: (a) exposing a substrate having oxygen-containing reaction sites to an environment of a first precursor of an organometallic compound, which contains a metal atom and ligand groups, so as to form a chemisorption layer of the first precursor on the substrate; (b) exposing the chemisorption layer on the substrate to a non-free radical environment of a second precursor after step (a) so as to remove the ligand groups of the chemisorption layer that are unreacted in step (a) and so as to convert the chemisorption layer into a metal oxide layer; and (c) after step (b), exposing the metal oxide layer on the substrate to a free radical-containing gas containing free radicals so as to remove the ligand groups of the chemisorption layer that are left unreacted in step (b).

Abstract translation: 制造金属氧化物层的方法包括：（a）将具有含氧反应位点的底物暴露于含有金属原子和配体基团的有机金属化合物的第一前体的环境中，以形成化学吸附层 的基质上的第一种前体; （b）在步骤（a）之后将底物上的化学吸附层暴露于第二前体的非自由基环境，以除去步骤（a）中未反应的化学吸附层的配体基团，以便转化 化学吸附层转化为金属氧化物层; 和（c）在步骤（b）之后，将衬底上的金属氧化物层暴露于含有自由基的含自由基的气体中，以去除在步骤（b）中未反应的化学吸附层的配体基团。

公开(公告)号：US20050263807A1

公开(公告)日：2005-12-01

申请号：US11103322

申请日：2005-04-11

Applicant: Tai-Bor Wu ,  Chun-Kai Huang

Inventor： Tai-Bor Wu ,  Chun-Kai Huang

IPC: H01L21/02 ,  H01L21/8239 ,  H01L29/76

CPC classification number: H01L28/65 ,  H01L28/55

Abstract: A semiconductor device includes a MOS transistor, and a ferroelectric capacitor formed on the MOS transistor and including upper and lower electrode layers and a dielectric layer sandwiched between the upper and lower electrode layers. Each of the upper and lower electrode layers is made from a Pt—PtOx material, in which x is an integer from 1 to 2, and the weight percentage of PtOx based on the total weight of the Pt—PtOx material is in an amount ranging from 50-100%.

Abstract translation: 半导体器件包括MOS晶体管和形成在MOS晶体管上并包括上电极层和下电极层的铁电电容器和夹在上电极层和下电极层之间的电介质层。 上电极层和下电极层中的每一个由Pt-PtO x x材料制成，其中x是1至2的整数，并且PtO x x的重量百分比 基于Pt-PtO xS材料的总重量为50-100％。