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公开(公告)号：US20210091770A1
公开(公告)日：2021-03-25
申请号：US17112450
申请日：2020-12-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Feng Wei KUO , Chewn-Pu JOU , Huan-Neng CHEN , Lan-Chou CHO , Robert Bogdan STASZEWSKI , Seyednaser POURMOUSAVIAN
Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.
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公开(公告)号：US20150236644A1
公开(公告)日：2015-08-20
申请号：US14701175
申请日：2015-04-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ying-Ta LU , Hsien-Yuan LIAO , Chi-Hsien LIN , Hsiao-Tsung YEN , Ho-Hsiang CHEN , Chewn-Pu JOU
IPC: H03B5/12
CPC classification number: H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1296
Abstract: An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and a first, second, third, and fourth inductive elements. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The first and second inductive elements are electrically coupled to the first output nodes, respectively. The third inductive element is electrically coupled to one of the second output nodes and DC-biased and magnetically coupled to the first inductive element. The fourth inductive element is electrically coupled to the other of the second output nodes and DC-biased and magnetically coupled to the second inductive element.
Abstract translation: 公开了一种装置，其包括第一交叉耦合晶体管对，第二交叉耦合晶体管对，至少一个电容单元以及第一，第二，第三和第四电感元件。 第一交叉耦合晶体管对和第二交叉耦合晶体管对分别耦合到一对第一输出节点和一对第二输出节点。 所述至少一个电容单元耦合到所述一对第一输出节点和所述一对第二输出节点中的至少一个。 第一和第二电感元件分别电耦合到第一输出节点。 第三感应元件电耦合到第二输出节点中的一个并被直流偏置并且磁耦合到第一电感元件。 第四电感元件电耦合到第二输出节点中的另一个，并且被直流偏置并且磁耦合到第二电感元件。
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公开(公告)号：US20140368285A1
公开(公告)日：2014-12-18
申请号：US13918489
申请日：2013-06-14
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ying-Ta LU , Hsien-Yuan LIAO , Chi-Hsien LIN , Hsiao-Tsung YEN , Ho-Hsiang CHEN , Chewn-Pu JOU
IPC: H03B5/12
CPC classification number: H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1296
Abstract: An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and an inductive unit. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The inductive unit is coupled to the first cross-coupled transistor pair at the first output nodes and coupled to the second cross-coupled transistor pair at the second output nodes. The inductive unit generates mutual magnetic coupling between one of the first output nodes and one of the second output nodes and between the other of the first output nodes and the other of the second output nodes.
Abstract translation: 公开了一种包括第一交叉耦合晶体管对，第二交叉耦合晶体管对，至少一个电容单元和电感单元的装置。 第一交叉耦合晶体管对和第二交叉耦合晶体管对分别耦合到一对第一输出节点和一对第二输出节点。 所述至少一个电容单元耦合到所述一对第一输出节点和所述一对第二输出节点中的至少一个。 感应单元在第一输出节点处耦合到第一交叉耦合晶体管对并且在第二输出节点耦合到第二交叉耦合晶体管对。 感应单元在第一输出节点之一和第二输出节点中的一个之间以及第一输出节点中的另一个和第二输出节点的另一个之间产生互耦合。
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公开(公告)号：US20140252546A1
公开(公告)日：2014-09-11
申请号：US13789825
申请日：2013-03-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hsiao-Tsung YEN , Ying-Ta LU , Ho-Hsiang CHEN , Chewn-Pu JOU
IPC: H01L27/02
CPC classification number: H01L27/0207 , H01L23/5223 , H01L2924/0002 , H01L2924/00
Abstract: A capacitor structure comprising semiconductor substrate and a matrix of capacitor units formed over the semiconductor substrate each capacitor unit. The matrix includes an interior structure comprised of one or more vertical plates, each vertical plate of the interior structure formed from a plurality of conductive portions connected vertically to each other, an exterior structure comprised of one or more vertical plates, each vertical plate of the exterior structure formed from a plurality of conductive portions connected vertically to each other, the exterior structure substantially encompassing the interior structure, and insulative material separating the interior and exterior structures. The structure also comprises a switching mechanism included in the capacitor structure to switch between ones of the plural capacitor units.
Abstract translation: 一种电容器结构，包括半导体衬底和形成在半导体衬底上的每个电容器单元上的电容器单元的矩阵。 该矩阵包括由一个或多个垂直板构成的内部结构，内部结构的每个垂直板由彼此垂直连接的多个导电部分形成，外部结构由一个或多个垂直板组成，每个垂直板 外部结构由彼此垂直连接的多个导电部分形成，外部结构基本上包围内部结构，以及分离内部和外部结构的绝缘材料。 该结构还包括在电容器结构中包括的切换机构以在多个电容器单元中的一个之间切换。
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公开(公告)号：US20220149146A1
公开(公告)日：2022-05-12
申请号：US17585372
申请日：2022-01-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Feng Wei KUO , Chewn-Pu JOU , Huan-Neng CHEN , Lan-Chou CHO , Robert Bogdan STASZEWSKI
IPC: H01L49/02 , H01F27/28 , H03L7/085 , H01L23/522 , H03L7/099 , B01D1/00 , B01D1/12 , C02F1/04 , C02F11/12 , C02F11/18
Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20210175187A1
公开(公告)日：2021-06-10
申请号：US17182155
申请日：2021-02-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Feng Wei KUO , Wen-Shiang LIAO , Chewn-Pu JOU , Huan-Neng CHEN , Lan-Chou CHO , William Wu SHEN
IPC: H01L23/66 , H01L25/065 , H01L23/498 , H01L23/00 , H01L23/552 , H01L23/522 , H01L25/18
Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.
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公开(公告)号：US20200158960A1
公开(公告)日：2020-05-21
申请号：US16654623
申请日：2019-10-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Feng-Wei KUO , Lan-Chou CHO , Huan-Neng CHEN , Chewn-Pu JOU
Abstract: Disclosed are grating couplers having a high coupling efficiency for optical communications. In one embodiment, an apparatus for optical coupling is disclosed. The apparatus includes: a substrate; a grating coupler comprising a plurality of coupling gratings over the substrate, wherein each of the plurality of coupling gratings extends in a first lateral direction and has a cross-section having a middle-raised shape in a second lateral direction, wherein the first and second lateral directions are parallel to a surface of the substrate and perpendicular to each other in a grating plane; and a cladding layer comprising an optical medium, wherein the cladding layer is filled in over the grating coupler.
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公开(公告)号：US20190058231A1
公开(公告)日：2019-02-21
申请号：US16168649
申请日：2018-10-23
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chewn-Pu JOU , Wen-Shiang LIAO
CPC classification number: H01P3/16 , G02B6/122 , G02B6/1228 , G02B6/132 , G02B6/4274 , G02B6/4298 , G02F1/011 , G02F1/025 , H01L2224/18
Abstract: A semiconductor structure is disclosed that includes a dielectric waveguide, a first transmission electrode and a second transmission electrode, and a first receiver electrode and a second receiver electrode. The first transmission electrode and the second transmission electrode that are disposed over and below the dielectric waveguide, respectively, and the first transmission electrode and the second transmission electrode are symmetric with respect to the dielectric waveguide. The first receiver electrode and a second receiver electrode that are disposed over and below the dielectric waveguide, respectively, and the first receiver electrode and the second receiver electrode are symmetric with respect to the dielectric waveguide. The dielectric waveguide is configured to receive a transmission signal from a driver circuit through the first transmission electrode and to transmit the received transmission signal to a receiver circuit through the first receiver electrode.
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公开(公告)号：US20180226329A1
公开(公告)日：2018-08-09
申请号：US15943680
申请日：2018-04-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Wen-Shiang LIAO , Chewn-Pu JOU
IPC: H01L23/498 , H01G4/30 , H01G4/38 , H01L23/00 , H01G4/005 , H01L49/02 , H01L23/538 , H01L27/08 , H01L23/522
CPC classification number: H01L23/49822 , H01G4/005 , H01G4/306 , H01G4/38 , H01L23/49816 , H01L23/49827 , H01L23/5223 , H01L23/5389 , H01L24/19 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L27/0805 , H01L28/60 , H01L28/90 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/24195 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/83005 , H01L2224/92244 , H01L2924/19041 , H01L2924/19105
Abstract: A method of forming a semiconductor device includes forming a first redistribution line on a substrate; forming a plurality of first vertical conductive structures on the first redistribution line and electrically coupled to the first redistribution line; forming a plurality of second vertical conductive structures on the substrate, wherein the first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and the second vertical conductive structures are spaced apart from the first redistribution line; attaching a device die on the substrate; applying a molding compound in a molding layer overlying the substrate to surround the device die; and forming a second redistribution line on the molding layer, wherein the second redistribution line is electrically coupled to the second vertical conductive structures.
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20.发明申请公开(公告)号：US20170278808A1
公开(公告)日：2017-09-28
申请号：US15621084
申请日：2017-06-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Shiang LIAO , Chewn-Pu JOU , Feng Wei KUO
IPC: H01L23/66 , H01L21/48 , H01L23/00 , H01L23/498 , H01L23/522 , H01L23/528 , H01L23/538 , H01L23/552 , H01L21/56
CPC classification number: H01L23/66 , H01L21/4853 , H01L21/568 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5227 , H01L23/528 , H01L23/5389 , H01L23/552 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L2223/6616 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/05647 , H01L2224/11334 , H01L2224/1146 , H01L2224/11849 , H01L2224/12105 , H01L2224/131 , H01L2224/24137 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/83005 , H01L2224/83101 , H01L2224/92244 , H01L2924/14 , H01L2924/1421 , H01L2924/15311 , H01L2924/18162 , H01Q9/0407 , H01L2924/00014 , H01L2924/014 , H01L2224/02379
Abstract: A method for forming an integrated fan-out package includes depositing an adhesive layer on a carrier, forming a back-side buffer layer over the adhesive layer, forming a back-side redistribution metal layer on the back-side buffer layer, wherein the back-side redistribution metal layer includes one or more ground plane structures, forming one or more through-insulator vias (TIVs) and one or more cavity sidewalls on the one or more ground plane structures, placing a radio frequency (RF) integrated circuit (IC) die on the back-side buffer layer, laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with a molding compound, thus forming an interim substrate, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities, and forming a top-side redistribution (RDL) wiring structure on the interim substrate, the top-side RDL wiring structure including one or more integrated patch antenna structure, wherein the one or more integrated patch antenna structure is coupled to the RF IC die and each of the one or more integrated patch antenna structure is positioned over one of the antenna cavities.
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