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    Integrated circuit and operating method thereof
    11.
    发明授权
    Integrated circuit and operating method thereof 有权

    公开(公告)号：US10978144B2

    公开(公告)日：2021-04-13

    申请号：US16572625

    申请日：2019-09-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-En Huang ,  Hidehiro Fujiwara ,  Jui-Che Tsai ,  Yen-Huei Chen ,  Yih Wang

    IPC: G11C7/00 ,  G11C11/419 ,  H01L27/11 ,  G11C5/06 ,  G11C11/418

    Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    12.
    发明申请
    MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210066319A1

    公开(公告)日：2021-03-04

    申请号：US16805868

    申请日：2020-03-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Hsun Chiu ,  Yih Wang

    IPC: H01L27/112 ,  H01L23/525

    Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a transistor, a first embedded insulating structure and a second embedded insulating structure. The transistor is formed on a substrate, and includes a gate structure, channel structures, a source electrode and a drain electrode. The channel structures penetrate through the gate structure, and are in contact with the source and drain electrodes. The first and second embedded insulating structures are disposed in the substrate, and overlapped with the source and drain electrodes. The first and second embedded insulating structures are laterally spaced apart from each other by a portion of the substrate lying under the gate structure.

    Power Management Circuit for an Electronic Device
    14.
    发明申请
    Power Management Circuit for an Electronic Device 有权
    电子设备电源管理电路

    公开(公告)号：US20170040042A1

    公开(公告)日：2017-02-09

    申请号：US14980287

    申请日：2015-12-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hektor Huang ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Chia-En Huang ,  Chiting Cheng ,  Chen-Lin Yang ,  Jung-Ping Yang ,  Cheng Hung Lee

    IPC: G11C5/14 ,  H02J4/00

    CPC classification number: G11C5/147 ,  H02J4/00

    Abstract: A power management circuit for an electronic device is disclosed that sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.

    Abstract translation: 公开了一种用于电子设备的电源管理电路，其顺序地激活和/或去激活电子设备的电子电路。 功率管理电路提供第一组一个或多个电路功率管理信号以激活和/或去激活来自电子电路之间的第一电子电路。 此后，电源管理电路从一个或多个电路电源管理信号的第二组中提供相应的功率管理信号，其对应于已经被第一组的第一组激活和/或去激活的第一电子电路的一部分 一个或多个电路功率管理信号，用于激活和/或去激活来自电子电路的第二电子电路的一部分。 功率管理电路以类似的方式继续顺序提供一个或多个电路功率管理信号中的每一个，直到电子设备的电子电路已经被激活和/或去激活为止。

    Dynamic memory cell replacement using column redundancy
    15.
    发明授权
    Dynamic memory cell replacement using column redundancy 有权
    使用列冗余的动态内存单元更换

    公开(公告)号：US09218262B2

    公开(公告)日：2015-12-22

    申请号：US13972082

    申请日：2013-08-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Fu-An Wu ,  Jung-Ping Yang ,  Chia-En Huang ,  Cheng Hung Lee

    IPC: G11C29/00 ,  G06F11/25

    CPC classification number: G06F11/25 ,  G11C29/00 ,  G11C29/808 ,  G11C29/848

    Abstract: A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.

    Abstract translation: 存储器芯片包括具有多个存储器列的主存储器阵列，与主存储器阵列相关联的冗余存储器列，以及命中逻辑电路，其被配置为通过命中中的多个命中逻辑单元产生多个命中逻辑信号 逻辑电路，用于在存储器列之一中动态替换存储器列之一中的有缺陷的存储器单元，以便在存储器阵列运行时由冗余存储器列进行动态替换。

    Integrated chip and method of forming thereof
    19.
    发明授权
    Integrated chip and method of forming thereof 有权

    公开(公告)号：US11424339B2

    公开(公告)日：2022-08-23

    申请号：US17081012

    申请日：2020-10-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Meng-Han Lin ,  Chia-En Huang

    IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3215 ,  H01L21/762 ,  H01L29/06

    Abstract: An integrated chip includes a substrate, an isolation structure and a poly gate structure. The isolation structure includes dielectric materials within the substrate and having sidewalls defining an active region. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first and second widths. The poly gate structure extends over the channel region. The poly gate structure includes a first doped region having a first type of dopants and a second doped region having a second type of dopants. The second type is different from the first type.

    Integrated circuit layout, method, structure, and system
    20.
    发明授权
    Integrated circuit layout, method, structure, and system 有权

    公开(公告)号：US11342341B2

    公开(公告)日：2022-05-24

    申请号：US17025563

    申请日：2020-09-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Meng-Sheng Chang ,  Chien-Ying Chen ,  Chia-En Huang ,  Yih Wang

    IPC: H01L27/112 ,  G06F30/392 ,  H01L23/528 ,  H01L23/522

    Abstract: A method of generating an IC layout diagram includes positioning a first active region between second and third active regions, intersecting the first active region with first through fourth gate regions to define gate locations of first and second anti-fuse bits, aligning first and second conductive regions between the first and second active regions, thereby intersecting the first conductive region with the first gate region and the second conductive region with the fourth gate region, and aligning third and fourth conductive regions between the first and third active regions, thereby either intersecting the third and fourth conductive regions with the first and third gate regions, or intersecting the third and fourth conductive regions with the second and fourth gate regions. At least one of positioning or intersecting the first active region, or aligning the first and second or third and fourth conductive regions is executed by a processor.

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