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公开(公告)号：US20230326508A1
公开(公告)日：2023-10-12
申请号：US18321196
申请日：2023-05-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： MingYuan Song , Shy-Jay Lin , Chien-Min Lee , William Joseph Gallagher
CPC classification number: G11C11/1675 , G01R33/093 , G11C11/161 , H10B61/22 , H10N50/10 , H10N50/85 , H10N52/01 , H10N52/80
Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a shared selector layer coupled to the first terminal.
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公开(公告)号：US11723218B2
公开(公告)日：2023-08-08
申请号：US17216162
申请日：2021-03-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shy-Jay Lin , Chien-Min Lee , Hiroki Noguchi , Mingyuan Song , Yen-Lin Huang , William Joseph Gallagher
IPC: H01L21/00 , H10B61/00 , H01L23/528 , H01L21/768 , H01L21/8234
CPC classification number: H10B61/22 , H01L21/76898 , H01L21/823475 , H01L23/528
Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.
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公开(公告)号：US11706999B2
公开(公告)日：2023-07-18
申请号：US17369484
申请日：2021-07-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Min Lee , Shy-Jay Lin , Yen-Lin Huang , MingYuan Song , Tung Ying Lee
CPC classification number: H01L43/04 , H01L27/228 , H01L43/10 , H01L43/14
Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.
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公开(公告)号：US20220223785A1
公开(公告)日：2022-07-14
申请号：US17369484
申请日：2021-07-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Min Lee , Shy-Jay Lin , Yen-Lin Huang , MingYuan Song , Tung Ying Lee
Abstract: Semiconductor device includes pair of active devices, composite spin Hall electrode, and a magnetic tunnel junction. Composite spin Hall electrode is electrically connected to pair of active devices. Magnetic tunnel junction is disposed on opposite side of composite spin hall electrode with respect to pair of active devices. Spin Hall electrode includes pair of heavy metal layers, and spacer layer disposed in between pair of heavy metal layers. Pair of heavy metal layers is made of a heavy metal in a metastable state. Spacer layer comprises first material different from the pair of heavy metal layers.
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公开(公告)号：US10964888B2
公开(公告)日：2021-03-30
申请号：US16840100
申请日：2020-04-03
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Pin-Ren Dai , Chung-Ju Lee , Chung-Te Lin , Chih-Wei Lu , Hsi-Wen Tien , Tai-Yen Peng , Chien-Min Lee , Wei-Hao Liao
Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.
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Patent Agency Ranking
公开(公告)号：US10276794B1
公开(公告)日：2019-04-30
申请号：US15799416
申请日：2017-10-31
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Tai-Yen Peng , Hui-Hsien Wei , Wei-Chih Wen , Pin-Ren Dai , Chien-Min Lee , Han-Ting Tsai , Jyu-Horng Shieh , Chung-Te Lin
Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.
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公开(公告)号：US20240389472A1
公开(公告)日：2024-11-21
申请号：US18786688
申请日：2024-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Lin Huang , MingYuan Song , Chien-Min Lee , Shy-Jay Lin , Chi-Feng Pai , Chen-Yu Hu , Chao-Chung Huang , Kuan-Hao Chen , Chia-Chin Tsai , Yu-Fang Chiu , Cheng-Wei Peng
IPC: H10N50/85 , C22C5/04 , H01F10/32 , H10B61/00 , H10N50/10 , H10N50/80 , H10N52/00 , H10N52/01 , H10N52/80
Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5 d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3 d orbitals.
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公开(公告)号：US12069958B2
公开(公告)日：2024-08-20
申请号：US18312372
申请日：2023-05-04
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Tai-Yen Peng , Hui-Hsien Wei , Wei-Chih Wen , Pin-Ren Dai , Chien-Min Lee , Sheng-Chih Lai , Han-Ting Tsai , Chung-Te Lin
CPC classification number: H10N50/01 , G11C11/161 , H10B61/20 , H10N50/10 , H10N50/80
Abstract: A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.
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公开(公告)号：US12022665B2
公开(公告)日：2024-06-25
申请号：US18335816
申请日：2023-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shy-Jay Lin , Chien-Min Lee , Hiroki Noguchi , MingYuan Song , Yen-Lin Huang , William Joseph Gallagher
IPC: H01L21/00 , H01L21/768 , H01L21/8234 , H01L23/528 , H10B61/00
CPC classification number: H10B61/22 , H01L21/76898 , H01L21/823475 , H01L23/528
Abstract: A device includes a substrate having a first side and a second side, a first transistor that includes a first gate over a first protrusion and a first source region and a first drain region interposing the first protrusion, a first buried contact disposed adjacent to the first protrusion and having at least a portion extending into the substrate, a first contact plug disposed over the first drain region, first conductive lines disposed over the first contact plug and electrically connecting to the first drain region by the first contact plug, first via penetrating through the substrate and connecting the first buried contact; and second conductive lines disposed over the second side of the substrate and electrically connecting to the first via. The first buried contact is electrically connecting to the first source region or the first gate.
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公开(公告)号：US11805705B2
公开(公告)日：2023-10-31
申请号：US17144958
申请日：2021-01-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shy-Jay Lin , Chien-Min Lee , MingYuan Song
Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction structure which may be strained and seedless and formed with a perpendicular magnetic anisotropy. A magnetic tunnel junction (MTJ) stack is disposed over the SOT induction structure. A spacer layer may decouple layers between the SOT induction structure and the MTJ stack or decouple layers within the MTJ stack. One end of the SOT induction structure may be coupled to a first transistor and another end of the SOT induction structure coupled to a second transistor.
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