公开(公告)号：US09087793B2

公开(公告)日：2015-07-21

申请号：US14103681

申请日：2013-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Han-Wen Liao ,  Wei-Tai Lin ,  Wen-Sheng Wang ,  Chih-Yu Lin ,  Cherng-Chang Tsuei ,  Chen-Hsiang Lu

IPC: H01L21/308

CPC classification number: H01L21/3088 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/32136 ,  H01L22/12 ,  H01L22/20

Abstract: A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.

Abstract translation: 提供了一种在蚀刻装置中蚀刻半导体器件的目标层的方法。 为了形成元件，该方法包括在半导体器件的目标层上形成光致抗蚀剂图案，其中光致抗蚀剂图案具有显影后检查临界尺寸（ADI CD）。 提供元件的目标蚀刻后检查临界尺寸（AEI CD），以及目标层的修剪时间。 提供蚀刻装置，并且基于ADI CD，目标AEI CD和修剪时间确定蚀刻装置的内壁上的保护层的形成时间。 形成预定形成时间的保护层，通过使用光致抗蚀剂图案作为掩模，对目标层进行修整时间的修整处理，以形成元件。

公开(公告)号：US12245412B2

公开(公告)日：2025-03-04

申请号：US18362786

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro Fujiwara ,  Wei-Min Chan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H10B10/00 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02

Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

公开(公告)号：US11778802B2

公开(公告)日：2023-10-03

申请号：US17320091

申请日：2021-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro Fujiwara ,  Wei-Min Chan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H10B10/00 ,  H01L27/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528

CPC classification number: H10B10/12 ,  H01L21/321 ,  H01L21/76838 ,  H01L23/5283 ,  H01L27/0207

Abstract: A device is disclosed that includes a fin structure disposed below a first metal layer, extending along a column direction, and corresponding to at least one transistor of a memory bit cell, a word line disposed in the first metal layer and extending along a row direction, a first metal island disposed in the first metal layer separated from the word line, and a first connection metal line disposed in a second metal layer above the first metal layer, extending along the column direction, and configured to couple a power supply through the first metal island to the fin structure. In a layout view, the first connection metal line is separated from the fin structure, and the fin structure crosses over the word line and the first metal island. A method is also disclosed herein.

公开(公告)号：US20180102163A1

公开(公告)日：2018-04-12

申请号：US15288342

申请日：2016-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Chen LIN ,  Wei-Min Chan ,  Chih-Yu Lin ,  Shih-Lien Linus Lu ,  Yen-Huei Chen

IPC: G11C11/419 ,  G11C11/418 ,  H04L9/32

CPC classification number: G11C11/419 ,  G09C1/00 ,  G11C7/20 ,  G11C7/24 ,  G11C11/413 ,  G11C11/418 ,  G11C2029/4402 ,  H04L9/3278

Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.

公开(公告)号：US09659620B2

公开(公告)日：2017-05-23

申请号：US14670241

申请日：2015-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Huei Chen ,  Hung-Jen Liao ,  Chih-Yu Lin ,  Jonathan Tsung-Yung Chang ,  Wei-Cheng Wu

IPC: G11C11/34 ,  G11C7/00 ,  G11C8/00 ,  G11C8/08 ,  G11C11/418

CPC classification number: G11C8/08 ,  G11C11/418

Abstract: An electronic device is disclosed that includes memory cells, a word line, a selection unit and a self-boosted driver. The memory cells are configured to store data. The word line is coupled to the memory cells. The selection unit is disposed at a first terminal of the word line, and is configured to transmit a selection signal to activate the word line according to one of a read command and a write command. The self-boosted driver is disposed at a second terminal of the word line, and is configured to pull up a voltage level of the word line according to a voltage level of the word line and a control signal.

公开(公告)号：US09142275B2

公开(公告)日：2015-09-22

申请号：US13665031

申请日：2012-10-31

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Li-Wen Wang ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/00 ,  G11C8/08 ,  G11C16/04 ,  G11C8/00 ,  G11C29/02 ,  G11C11/4063 ,  G11C7/00 ,  G11C29/12

CPC classification number: G11C8/08 ,  G11C7/00 ,  G11C8/00 ,  G11C11/4063 ,  G11C16/04 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1202

Abstract: Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal.

Abstract translation: 本公开的一些方面是一种方法。 在该方法中，字线电压被提供给字线，该字线耦合到多个存储器单元。 提供升压使能信号。 升压使能信号的状态表示字线上的预定位置的字线电压是否达到非零预定字线电压。 基于升压使能信号，字线电压被选择性地升压到升压的字线电压电平。

公开(公告)号：US11948627B2

公开(公告)日：2024-04-02

申请号：US17818386

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Sahil Preet Singh ,  Hsien-Yu Pan ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418 ,  H03K19/013

CPC classification number: G11C11/419 ,  G11C5/147 ,  G11C7/12 ,  G11C11/412 ,  G11C11/418 ,  H03K19/0136

Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

公开(公告)号：US11024633B2

公开(公告)日：2021-06-01

申请号：US16562299

申请日：2019-09-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hidehiro Fujiwara ,  Wei-Min Chan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  H01L21/321 ,  H01L21/768

Abstract: A device is disclosed that includes a memory bit cell coupled to a bit line, a word line, a pair of metal islands and a pair of connection metal lines. The word line is electrically coupled to the memory bit cell and is elongated in a first direction. The pair of metal islands are disposed at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are elongated in a second direction, and are configured to electrically couple the pair of metal islands to the memory bit cell, respectively. The pair of connection metal lines are separated from the bit line in a layout view. A method of fabricating the device is also provided.

公开(公告)号：US10964389B2

公开(公告)日：2021-03-30

申请号：US16911049

申请日：2020-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

公开(公告)号：US10832765B2

公开(公告)日：2020-11-10

申请号：US16376640

申请日：2019-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: G11C11/419 ,  G11C11/412

Abstract: A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.