公开(公告)号：US11271083B2

公开(公告)日：2022-03-08

申请号：US16805862

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Jr-Hung Li ,  Tai-Chun Huang ,  Tze-Liang Lee ,  Chung-Ting Ko ,  Jr-Yu Chen ,  Wan-Chen Hsieh

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

公开(公告)号：US20210262090A1

公开(公告)日：2021-08-26

申请号：US17018797

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Chung-Ting Ko ,  Tsung-Hsun Yu ,  Tze-Liang Lee ,  Chi On Chui

IPC: C23C16/455 ,  H01L21/033 ,  H01L21/02 ,  C23C16/40

Abstract: In an embodiment, a method of manufacturing a semiconductor device includes preparing a deposition processing chamber by flowing first precursors to form a dielectric coat along an inner sidewall of the deposition processing chamber and flowing a second precursor to form a hydrophobic layer over the dielectric coat. In addition one or more deposition cycles are performed. Next, the second precursor is flowed again to repair the hydrophobic layer.

公开(公告)号：US20240429313A1

公开(公告)日：2024-12-26

申请号：US18476619

申请日：2023-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Cheng Shiau ,  Chung-Ting Ko ,  Ting-Hsiang Chang ,  Shu Ling Liao ,  Sung-En Lin ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A method includes etching a semiconductor region aside of a gate stack to form a recess, forming a dielectric layer at a bottom of the recess, selectively forming a first semiconductor layer at the bottom of the recess, and epitaxially growing a second semiconductor layer on the first semiconductor layer. A bottom surface of the first semiconductor layer forms an interface with a top surface of the dielectric layer, with the interface extending to opposing sides of the recess. The selectively forming the first semiconductor layer comprises a first deposition process performed under first process conditions. The second semiconductor layer is formed using a second deposition process under second process conditions. The second process conditions are different from the first process conditions.

公开(公告)号：US20240413157A1

公开(公告)日：2024-12-12

申请号：US18742480

申请日：2024-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Fong Lin ,  Wan Chen Hsieh ,  Chung-Ting Ko ,  Tai-Chun Huang

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

公开(公告)号：US20240363429A1

公开(公告)日：2024-10-31

申请号：US18771662

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41791

Abstract: A semiconductor device includes a fin disposed on a substrate, a first dielectric layer disposed over the fin, a first contact extending through the first dielectric layer to a first depth and electrically coupled to the fin, and a second contact extending through the first dielectric layer to a second depth different than the first depth. The first contact has a first bottom portion having a first cross-sectional shape profile. The second contact being electrically isolated from the fin and having a second bottom portion having a second cross-sectional shape profile different than the first cross-sectional shape profile. The semiconductor device also includes a first protective layer disposed along the first contact without being disposed on at least a portion of the first bottom portion of the first contact, and a second protective layer disposed along the second contact including along the second bottom portion of the second contact.

公开(公告)号：US20240079265A1

公开(公告)日：2024-03-07

申请号：US18151901

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Sung-En Lin ,  Chi On Chui

IPC: H01L21/762 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/66439 ,  H01L29/66545

Abstract: A method includes depositing a first material on a sidewall surface of a recess in a substrate, wherein the first material is a conductive material; after depositing the first material, depositing a second material on a bottom surface of the recess using a plasma-assisted deposition process; and after depositing the second material, removing the first material.

公开(公告)号：US20230335406A1

公开(公告)日：2023-10-19

申请号：US18341410

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Wan-Chen Hsieh ,  Chun-Ming Lung ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L21/3085 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02356 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/092

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20230154984A1

公开(公告)日：2023-05-18

申请号：US17742943

申请日：2022-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Tai-Jung Kuo ,  Sung-En Lin ,  Zhen-Cheng Wu ,  Chi On Chui

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

Abstract: In an embodiment, a device includes: first source/drain regions; a first insulating fin between the first source/drain regions, the first insulating fin including a first lower insulating layer and a first upper insulating layer; second source/drain regions; and a second insulating fin between the second source/drain regions, the second insulating fin including a second lower insulating layer and a second upper insulating layer, the first lower insulating layer and the second lower insulating layer including the same dielectric material, the first upper insulating layer and the second upper insulating layer including different dielectric materials.

公开(公告)号：US11532507B2

公开(公告)日：2022-12-20

申请号：US17169989

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Chen ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chung-Ting Ko ,  Jr-Hung Li ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/08

Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.

公开(公告)号：US20220328627A1

公开(公告)日：2022-10-13

申请号：US17402930

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hong Chang ,  Yi-Hsiu Liu ,  You-Ting Lin ,  Chih-Chung Chang ,  Kuo-Yi Chao ,  Jiun-Ming Kuo ,  Yuan-Ching Peng ,  Sung-En Lin ,  Chia-Cheng Chao ,  Chung-Ting Ko

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/768

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.