公开(公告)号：US20210242080A1

公开(公告)日：2021-08-05

申请号：US17238496

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Chiang Weng ,  Ping-Hao Lin ,  Fu-Cheng Chang

IPC: H01L21/768 ,  H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L21/311

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

公开(公告)号：US10804414B2

公开(公告)日：2020-10-13

申请号：US16390080

申请日：2019-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Hsiang Tseng ,  Chih-Fei Lee ,  Chia-Pin Cheng ,  Fu-Cheng Chang

IPC: H01L31/0216 ,  H01L31/0232 ,  H01L27/146 ,  H01L31/112

Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.

公开(公告)号：US10170515B2

公开(公告)日：2019-01-01

申请号：US15487573

申请日：2017-04-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Chun Lu ,  Ching-Hung Kao ,  Fu-Cheng Chang ,  Chia-Pin Cheng ,  Po-Chun Chiu

IPC: H01L27/146

Abstract: A semiconductor device includes a substrate and a device. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first well region, and the first well region includes a first shallow implantation region adjacent to the first surface and a first deep implantation region adjacent to the second surface, in which a dopant concentration of the first deep implantation region at the second surface is substantially equal to 0. The device is disposed on the first surface of the substrate and adjoins the first shallow implantation region.

公开(公告)号：US10157950B2

公开(公告)日：2018-12-18

申请号：US15866745

申请日：2018-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Hung Lee ,  Chia-Pin Cheng ,  Fu-Cheng Chang ,  Volume Chien ,  Ching-Hung Kao

IPC: H01L27/146

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.

公开(公告)号：US09373594B2

公开(公告)日：2016-06-21

申请号：US14179688

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Chih-Fei Lee ,  Fu-Cheng Chang ,  Chi-Cherng Jeng ,  Hsin-Chi Chen ,  Yuan-Ko Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/02 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2924/30101 ,  H01L2924/30105 ,  H01L2924/00014

Abstract: A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved.

Abstract translation: 提供了凸起下金属化的结构及其形成方法。 凸起下金属化具有从顶部观察到的圆形或具有大于90°的相邻边缘之间的角度的多边形形状的再分配通孔。 因此，可以提高稍后形成的金属层的台阶覆盖。

公开(公告)号：US09318368B2

公开(公告)日：2016-04-19

申请号：US14080631

申请日：2013-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Cheng Chang ,  Chai-Der Yen ,  Fu-Tsun Tsai ,  Chi-Cherng Jeng ,  Chih-Mu Huang

IPC: H01L21/76 ,  H01L21/762 ,  G03F1/00

CPC classification number: H01L21/76229 ,  G03F1/00 ,  H01L21/0274 ,  H01L21/3083

Abstract: In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is patterned by using a photomask to form at least one first hole and at least one second hole in the mask layer, in which a depth of the at least one first hole is different from a depth of the at least one second hole. The mask layer and the substrate are etched to form at least one first trench having a first depth and at least one second trench having a second depth, in which the first depth is different from the second depth. The remaining mask layer is removed. A first isolation layer and A second isolation layer are respectively formed in the at least one first trench and the at least one second trench.

Abstract translation: 在制造双浅沟槽隔离结构的方法中，提供衬底，并且在衬底上形成掩模层。 通过使用光掩模来对掩模层进行构图，以在掩模层中形成至少一个第一孔和至少一个第二孔，其中至少一个第一孔的深度不同于至少一个第二孔的深度 。 蚀刻掩模层和衬底以形成具有第一深度的至少一个第一沟槽和具有第二深度的至少一个第二沟槽，其中第一深度不同于第二深度。 剩下的掩模层被去除。 第一隔离层和第二隔离层分别形成在至少一个第一沟槽和至少一个第二沟槽中。

公开(公告)号：US11901305B2

公开(公告)日：2024-02-13

申请号：US17838375

申请日：2022-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Kuo-Hung Lee ,  Chih-Fei Lee ,  Fu-Cheng Chang ,  Ching-Hung Kao

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L29/00 ,  H01L21/02 ,  H10B12/00 ,  H01L21/311

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L23/528 ,  H01L23/5223 ,  H01L28/40 ,  H01L21/02063 ,  H01L21/31144 ,  H01L28/60 ,  H01L28/90 ,  H01L28/91 ,  H01L29/00 ,  H01L2223/5442 ,  H01L2223/5446 ,  H01L2223/54426 ,  H01L2223/54453 ,  H10B12/37

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

公开(公告)号：US11764062B2

公开(公告)日：2023-09-19

申请号：US16175819

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Hao Lin ,  Fu-Cheng Chang

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  G03F7/20 ,  G03F1/50 ,  G03F1/58 ,  G03F7/09 ,  G03F7/095 ,  H01L21/768 ,  G03F7/00

CPC classification number: H01L21/0337 ,  G03F1/50 ,  G03F1/58 ,  G03F7/094 ,  G03F7/095 ,  G03F7/70058 ,  G03F7/70466 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76807 ,  H01L2221/1021

Abstract: A method of forming a semiconductor structure is disclosed. A multi-layer structure is formed over a substrate. A photoresist stack with a stepped sidewall is formed on the multi-layer structure. A pattern of the photoresist stack is transferred to the multi-layer structure.

公开(公告)号：US11664403B2

公开(公告)日：2023-05-30

申请号：US16900683

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zen-Fong Huang ,  Fu-Cheng Chang

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14623 ,  H01L27/14685 ,  H01L27/14621 ,  H01L27/14627

Abstract: An image sensor device includes a substrate, a deep-trench isolation structure, a buffer layer, and a light blocking structure. The substrate has a photosensitive region. The deep-trench isolation structure is in the substrate and adjacent the photosensitive region. The buffer layer is over the photosensitive region and the deep-trench isolation structure. The light blocking structure is over the buffer layer. A bottom portion of the light blocking structure is embedded in the buffer layer.

公开(公告)号：US11362039B2

公开(公告)日：2022-06-14

申请号：US17068033

申请日：2020-10-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Kuo-Hung Lee ,  Chih-Fei Lee ,  Fu-Cheng Chang ,  Ching-Hung Kao

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L29/00 ,  H01L27/108 ,  H01L21/02

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.