公开(公告)号：US20240079239A1

公开(公告)日：2024-03-07

申请号：US18152454

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bau-Ming Wang ,  Liang-Yin Chen ,  Wei Tse Hsu ,  Jung-Tsan Tsai ,  Ya-Ching Tseng ,  Chunyii Liu

IPC: H01L21/225 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L21/2253 ,  H01L21/30625 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/0673

Abstract: A method includes implanting impurities in a semiconductor substrate to form an etch stop region within the semiconductor substrate; forming a transistor structure on a front side of the semiconductor substrate; forming a front-side interconnect structure over the transistor structure; performing a thinning process on a back side of the semiconductor substrate to reduce a thickness of the semiconductor substrate, wherein the thinning process is slowed by the etch stop region; and forming a back-side interconnect structure over the back side of the semiconductor substrate.

公开(公告)号：US20230282583A1

公开(公告)日：2023-09-07

申请号：US18302101

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53242 ,  H01L21/3215 ,  H01L21/76883 ,  H01L23/5226

Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

公开(公告)号：US11742210B2

公开(公告)日：2023-08-29

申请号：US17231670

申请日：2021-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Kuan-Yu Yeh ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/45 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/28518 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L29/45

Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

公开(公告)号：US11710659B2

公开(公告)日：2023-07-25

申请号：US17646024

申请日：2021-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/3115 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US20230061485A1

公开(公告)日：2023-03-02

申请号：US17463000

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Chun-Yen Chang ,  Chih-Kai Yang ,  Yu-Tien Shen ,  Ya Hui Chang

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/768

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

公开(公告)号：US20230058699A1

公开(公告)日：2023-02-23

申请号：US17982216

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Derek Chen ,  Liang-Yin Chen ,  Chien-I Kuo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324

Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

公开(公告)号：US11508831B2

公开(公告)日：2022-11-22

申请号：US17120869

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chien ,  Liang-Yin Chen ,  Yi-Hsiu Liu ,  Tsung-Lin Lee ,  Huicheng Chang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/51

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

公开(公告)号：US20220367254A1

公开(公告)日：2022-11-17

申请号：US17871042

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Wang ,  Po-Nan Yeh ,  U-Ting Chiu ,  Chun-Neng Lin ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.

公开(公告)号：US11502000B2

公开(公告)日：2022-11-15

申请号：US17001247

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3215 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

公开(公告)号：US20220359755A1

公开(公告)日：2022-11-10

申请号：US17813888

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Kuo-Ju Chen ,  Kai-Hsuan Lee ,  I-Hsieh Wong ,  Cheng-Yu Yang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Syun-Ming Jiang ,  Meng-Han Chou

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/764 ,  H01L21/768 ,  H01L29/49

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.