公开(公告)号：US10461089B2

公开(公告)日：2019-10-29

申请号：US16167879

申请日：2018-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L27/11521 ,  H01L21/762 ,  H01L27/11526 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11534 ,  H01L27/11548 ,  H01L23/528

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US10164181B2

公开(公告)日：2018-12-25

申请号：US15489863

申请日：2017-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Hsueh Yang ,  Yuan-Tai Tseng ,  Yi-Jen Tsai ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L43/08

Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode.

公开(公告)号：US10147794B2

公开(公告)日：2018-12-04

申请号：US15332115

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/11568 ,  H01L29/51

Abstract: The present disclosure relates to a split gate memory device. In some embodiments, the split gate memory device includes a memory gate arranged over a substrate, and a select gate arranged over the substrate. An inter-gate dielectric layer is arranged between sidewalls of the memory gate and the select gate that face one another. The inter-gate dielectric layer extends under the memory gate. A first dielectric is disposed above the inter-gate dielectric layer and is arranged between the sidewalls of the memory gate and the select gate.

公开(公告)号：US20180151579A1

公开(公告)日：2018-05-31

申请号：US15694098

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yu-Hsing Chang

IPC: H01L27/11521 ,  H01L27/11526 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/762 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/42328

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

公开(公告)号：US09978761B2

公开(公告)日：2018-05-22

申请号：US15216872

申请日：2016-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chyi Liu ,  Shih-Chang Liu ,  Sheng-Chieh Chen

IPC: H01L27/105 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/42328

Abstract: The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.

公开(公告)号：US09853091B2

公开(公告)日：2017-12-26

申请号：US15138436

申请日：2016-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yen Chou ,  Ching-Pei Hsieh ,  Chia-Shiung Tsai ,  Shih-Chang Liu

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L23/522 ,  G11C13/00

CPC classification number: H01L27/2463 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2418 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.

公开(公告)号：US20170345812A1

公开(公告)日：2017-11-30

申请号：US15216830

申请日：2016-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yen Chou ,  Chia-Shiung Tsai ,  Shih-Chang Liu ,  Yung-Chang Chang

IPC: H01L27/02 ,  H01L29/205 ,  H01L21/822 ,  H01L21/768 ,  H01L27/06 ,  H01L23/48 ,  H01L29/778 ,  H01L29/20

Abstract: A process for manufacturing an integrated circuit (IC) with a through via extending through a group III-V layer to a diode is provided. An etch is performed through the group III-V layer, into a semiconductor substrate underlying the group III-V layer, to form a via opening. A doped region is formed in the semiconductor substrate, through the via opening. Further, the doped region is formed with an opposite doping type as a surrounding region of the semiconductor substrate. The through via is formed in the via opening and in electrical communication with the doped region.

公开(公告)号：US09818935B2

公开(公告)日：2017-11-14

申请号：US15000289

申请日：2016-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/04 ,  H01L27/22

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/12

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.

公开(公告)号：US20170309682A1

公开(公告)日：2017-10-26

申请号：US15138436

申请日：2016-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Yen Chou ,  Ching-Pei Hsieh ,  Chia-Shiung Tsai ,  Shih-Chang Liu

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/2463 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2418 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: The present disclosure relates to an integrated circuits device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect line disposed within a lower inter-level dielectric (ILD) layer and an upper metal interconnect line disposed within an upper inter-level dielectric (ILD) layer. The integrated circuit device also has a memory cell array disposed between the lower metal interconnect line and the upper metal interconnect line, including memory cells arranged in rows and columns, the memory cells respectively includes a bottom electrode and a top electrode separated by a RRAM dielectric having a variable resistance. A bottom contact structure is disposed on the lower metal interconnect line and along sidewalls of the bottom electrode, electrically coupling the lower metal interconnect line and the bottom electrode.

公开(公告)号：US09768220B2

公开(公告)日：2017-09-19

申请号：US14253025

申请日：2014-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuan-Tai Tseng ,  Yu-Hsing Chang ,  Ming Chyi Liu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/14638 ,  H01L21/76232 ,  H01L27/14607 ,  H01L27/14616 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L27/14692 ,  H01L29/0649

Abstract: Some embodiments of the present disclosure relate to a deep trench isolation structure. This deep trench isolation structure is formed on a semiconductor substrate having an upper semiconductor surface. A deep trench, which has a deep trench width as measured between opposing deep trench sidewalls, extends into the semiconductor substrate beneath the upper semiconductor surface. A fill material is formed in the deep trench, and a dielectric liner is disposed on a lower surface and sidewalls of the deep trench to separate the fill material from the semiconductor substrate. A shallow trench region has sidewalls that extend upwardly from the sidewalls of the deep trench to the upper semiconductor surface. The shallow trench region has a shallow trench width that is greater than the deep trench width. A dielectric material fills the shallow trench region and extends over top of the conductive material in the deep trench.