公开(公告)号：US20250031434A1

公开(公告)日：2025-01-23

申请号：US18353389

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Jih-Churng Twu ,  Su-Chun Yang ,  Shih-Peng Tai ,  Yu-Hao Kuo

IPC: H01L21/822 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

公开(公告)号：US20240096830A1

公开(公告)日：2024-03-21

申请号：US18151663

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Yi Huang ,  Yu-Hung Lin ,  Wei-Ming Wang ,  Chen Chen ,  Shih-Peng Tai ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L21/304 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/3043 ,  H01L24/03 ,  H01L24/80 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0221 ,  H01L2224/03019 ,  H01L2224/03831 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/08145 ,  H01L2224/80007 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/3512

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

公开(公告)号：US20240096722A1

公开(公告)日：2024-03-21

申请号：US18152539

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Kuo-Chung Yee ,  Chia-Hui Lin ,  Shih-Peng Tai

IPC: H01L23/31 ,  H01L21/321 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3128 ,  H01L21/32115 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/32245 ,  H01L2924/15311

Abstract: In an embodiment, a package includes a first device and a second device attached to a first redistribution structure, wherein the second device includes a second redistribution structure, a first die disposed over the second redistribution structure, a first encapsulant extending along sidewalls of the first die, a first via extending through the first encapsulant, a third redistribution structure disposed over the first encapsulant and including a first metallization pattern connecting to the first via, a second die disposed over the third redistribution structure, and a second encapsulant extending along sidewalls of the second die, the first die and the second die being free of through substrate vias. The package also includes a third encapsulant disposed over the first redistribution structure and surrounding sidewalls of the first device and the second device, wherein top surfaces of the second encapsulant and the third encapsulant are level with each other.

公开(公告)号：US11289398B2

公开(公告)日：2022-03-29

申请号：US16805869

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hui Wang ,  Der-Chyang Yeh ,  Shih-Peng Tai ,  Tsung-Shu Lin ,  Yi-Chung Huang

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A package structure including a substrate, a semiconductor device, a heat spreader, and an adhesive layer is provided. The semiconductor device is bonded onto the substrate, wherein an angle θ is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°

公开(公告)号：US09812381B1

公开(公告)日：2017-11-07

申请号：US15201604

申请日：2016-07-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsi Wu ,  Chun-Yi Liu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Shih-Peng Tai ,  Chuen-De Wang

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/49527 ,  H01L21/4821 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/4952 ,  H01L23/49589 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19011

Abstract: An integrated fan-out package is described. The integrated fan-out package comprises a first die and a second die arranged adjacent to each other. A molding compound encapsulates the first and second dies. A redistribution structure is disposed over the molding compound and on the first and second dies. The redistribution structure comprises a first connection structure electrically connected to the first die, a second connection structure electrically connected to the second die and an inter-dielectric layer located between the first and second connection structures and separating the first connection structure from the second connection structure. The ball pad is disposed on the redistribution structure and electrically connected with the first die or the second die. The bridge structure is disposed on the first connection structure and on the second connection structure and electrically connects the first die with the second die.